ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 92

• Manufacturer Part Number: ZL50404GDC
• Description: Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.7.11
CPU Address:h60A
Accessed by CPU (R/W)
13.3.7.12
I²C Address 0FF, CPU Address:h60B
Accessed by CPU and I²C (R/W)
This register is used in unmanaged mode only. Before requesting that the ZL50404 updates the EEPROM device,
the correct checksum needs to be calculated and written into this checksum register.
The checksum formula is:
When the ZL50404 boots from the EEPROM the checksum is calculated and the value must be zero. If the
checksum is not zeroed the ZL50404 does not start and pin CHECKSUM_OK is set to zero.
13.3.7.13
CPU Address:h610
Accessed by CPU (R/W)
In slot time (512 bit time). LHB packet will be sent out to the remote device if no other packet is transmitted in half
this period. The receiver will trigger LHB timeout interrupt if not receiving any good packet in this period.
13.3.7.14
CPU Address:h611, h612
Accessed by CPU (R/W)
The LHB frame uses MAC control frame format (same as flow control frame.) The register here defines the
operation code (we recommend h00-12).
Bit [0]:
Bit [1]:
Bit [7:2]:
Bit [7:0]:
DEVICE Mode
LHBTimer – Link Heart Beat Timeout Timer
LHBReg0, LHBReg1 - Link Heart Beat OpCode
CHECKSUM - EEPROM Checksum
FF
i = 0
Reserved
CPU Interrupt Polarity
0: Negative Polarity
1: Positive Polarity (Default)
Reserved
Checksum content (Default 0)
I²C register = 0
Zarlink Semiconductor Inc.
ZL50404
92
Data Sheet