ZL50404GDC ZARLINK [Zarlink Semiconductor Inc], ZL50404GDC Datasheet - Page 72

• Manufacturer Part Number: ZL50404GDC
• Description: Lightly Managed/Unmanaged 5-Port 10/100M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.4.2
CPU Address:h301
Accessed by CPU (R/W)
13.3.4.3
CPU Address:h302
Accessed by CPU (R/W)
13.3.4.4
CPU Address:h303
Accessed by CPU (R/W)
13.3.4.5
CPU Address:h304
Accessed by CPU (R/W)
13.3.4.6
CPU Address:h305
Accessed by CPU (R/W)
13.3.4.7
CPU Address:h306
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00)
-
-
1: Mask the interrupt
0: Unmask the interrupt (Enable interrupt)
Bit [0]:
Bit [1]:
MAC1 – CPU MAC address byte 1
MAC2 – CPU MAC address byte 2
MAC3 – CPU MAC address byte 3
MAC4 – CPU MAC address byte 4
MAC5 – CPU MAC address byte 5
INT_MASK0 – Interrupt Mask
Bit [7:0]:
Bit [7:0]:
Bit [7:0]:
Bit [7:0]:
Bit [7:0]:
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Byte 2 of the CPU MAC address (Default 0)
Byte 1 of the CPU MAC address (Default 0)
Byte 4 of the CPU MAC address (Default 0)
Byte 5 of the CPU MAC address (Default 0)
Byte 3 of the CPU MAC address (Default 0)
Zarlink Semiconductor Inc.
ZL50404
72
Data Sheet