ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 108

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.10.3
CPU Address E02, E03
Accessed by CPU (RO)
12.3.10.4
CPU Address E10-E14
Accessed by CPU (R/W)
Disable timeout reset on selected state machine status.
See Programming Timeout Reset application note, ZLAN-41, for more information.
12.3.10.5
CPU Address E80-E83
Accessed by CPU (RO)
12.3.10.6
CPU Address E90+n
Accessed by CPU (RO)
Bits [15:0]:
Bits [23:16]:
Bits [31:20]:
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
TESTOUT0, TESTOUT1 – Testmux Output [7:0], [15:8]
MASK0-MASK4 – Timeout Reset Mask
BOOTSTRAP0 – BOOTSTRAP3
PRTFSMST0~3,8,9
TX FSM NOT idle for 5 sec
TX FIFO control NOT idle for 5 sec
RX SFD detection NOT idle for 5 sec
RXINF NOT idle for 5 sec
PTCTL NOT idle for 5 sec
Bootstrap value from TSTOUT[15:0]:
Bootstrap value from M[3:0]_TXEN
Reserved
31
Bit [6:0]: TSTOUT[6:0]
Bit [8:7]: Invert of TSTOUT[8:7]
Bit [9]: TSTOUT[11]
Bit [10]: TSTOUT[9]
Bit [11]: TSTOUT[10]
Bit [14:12]: TSTOUT[14:12]
Bit [15]: Always 0
Bit [16]: M0_TXEN
Bit [17]: M1_TXEN
...
Bit [19]: M3_TXEN
BT3
23
Zarlink Semiconductor Inc.
BT2
ZL50405
108
15
BT1
BT0
0
Data Sheet