ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 73

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Port 8: (CPU Port)
Port 9: (MMAC Port)
Bits [1:0]:
Bit [2]:
Bits [4:3]:
Bit [5]:
Bit [6]:
Bit [7]:
Bit [0]:
Bit [1]:
Reserved
0: Disable (Default)
1: Enable
Should be enabled only in serial mode and disabled in 8/16-bit mode.
Enable insertion of 2-byte CPU information in CPU frame packet in Serial + MII
mode
00: No information is inserted
01: Insert 2-byte of CPU information
10: Reserved
11: Insert 6-byte of padding + 2-byte of CPU information (Default)
In port-based VLAN mode, the CPU MII interface must be in “No information is
inserted” mode (ECR4P8[4:3]='00'). In tagged-based VLAN mode, the CPU MII
interface supports all three modes (0,2,8 bytes insertion).
Frame loopback.
0: Disable frame from sending back to its source port. (Default)
1: Allow frame to send back to its source port
In a regular ethernet switch, a packet should never be receive and forwarded to
the same port. Setting the bit allows it to happen.
This is not the same as an ingress MAC loopback. The destination MAC address
has to be stored (learned) in the MCT and associated with the originating source
port. The frame loopback will only work for unicast packets.
Reserved
Soft reset.
0: Normal operation (Default)
1: Reset. Not self clearing.
Reserved
Enable RXCLK output. Active high
0: Disable (Default)
1: M9_RXCLK pin becomes output in MII mode
Note: To configure port 9 with the device providing the interface clocks, you need
to tie M9_RXCLK to M9_MTXCLK externally as M9_MTXCLK is not a bidirectional
clock.
Enable special write to 2 registers in a single write operation.
Zarlink Semiconductor Inc.
ZL50405
73
Data Sheet