ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 85

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ZL50405GDC

Manufacturer Part Number
ZL50405GDC
Description
Managed5-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
12.3.4.17
CPU Address:h338-339
Accessed by CPU, (RO)
CPU Queue insertion command
12.3.4.18
CPU Address:h33A-33E
Accessed by CPU, (R/W)
CPU Queue insertion command
12.3.4.19
CPU Address:h33f
Accessed by CPU, (R/W)
CPU receive queue status
Bits [14:0]:
Bits [30:15]
Bits [38:32]
Bits [14:0]:
Bit [15]:
Bit [0]:
Bit [1]:
Bit [2]:
CPUGRNHDL0 - CPUGRNHDL1 – CPU Allocated Granule Pointer
CPURLSINFO0 - CPURLSINFO4 – Receive Queue Status
CPUGRNCTR – CPU Granule Control
Allocate granule to the CPU if set to one. Otherwise, do not allocate any resource.
Read allocated granule (at rising edge only)
Release info valid (will be processed at rising edge only)
Granule pointer.
Pointer valid
Header pointer
Tail pointer
Number of granules for the release
CR4
15
CG1
CR3
Zarlink Semiconductor Inc.
ZL50405
CR2
85
CG0
CR1
0
CR0
0
Data Sheet

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