ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 65

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ZL50405GDC

Manufacturer Part Number
ZL50405GDC
Description
Managed5-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
PRTQOSST8A
PRTQOSST8B
PRTQOSST9A
PRTQUSST9B
CLASSQOSST
PRTINTCTR
QMCTRLn
QCTRL
BMBISTR0
BMBISTR1
BMControl
BUFF_RST
FCBHEADPTR0
FCB_HEAD_PTR1
FCB_TAIL_PTR0
FCB_TAIL_PTR1
FCB_NUM0
FCB_NUM1
BM_RLSFF_CTRL
BM_RLSFF_INFO0
BM_RLSFF_INFO1
BM_RLSFF_INFO2
BM_RLSFF_INFO3
BM_RLSFF_INFO4
BM_RLSFF_INFO5
F. System Control
GCR
DCR
DCR1
Register
CPU Port QOS and Queue
Status A
CPU Port QOS and Queue
Status B
MMAC Port QOS and
Queue Status A
MMAC Port QOS and
Queue Status B
Class Buffer Status
Buffer Interrupt Status
Ports Queue Control Status
Ports Queue Control
Memory bist result
Memory bist result
Memory control
Buffer Reset Pool
FCB Head Pointer [7:0]
FCB Head Pointer [15:8]
FCB Tail Pointer [7:0]
FCB Tail Pointer [15:8]
FCB Number [7:0]
FCB Init Start and FCB
Number [14:8]
Read control register
Bm_rlsfifo_info[7:0]
Bm_rlsfifo_info[15:8]
Bm_rlsfifo_info[23:16]
Bm_rlsfifo_info[31:24]
Bm_rlsfifo_info[39:32]
Fifo_cnt[2:0],Bm_rlsfifo_inf
o[44:40]
Global Control Register
Device Control Register
Device Control Register 1
Table 13 - Register Description (continued)
Description
Zarlink Semiconductor Inc.
ZL50405
65
CPU Addr
EB0+n
(Hex)
EAD
EBD
ECC
ECD
EAA
EAB
EAC
EBA
EBB
EBC
EC0
EC1
EC2
EC3
EC4
EC5
EC6
EC7
EC8
EC9
ECA
ECB
EA8
EA9
F00
F01
F02
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
R/O
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
(Hex)
Addr
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
I²C
Default
000
000
000
00F
000
000
000
000
000
000
006
000
000
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Data Sheet
(n=0..3,8,
Notes
9)

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