ZL50405GDC ZARLINK [Zarlink Semiconductor Inc], ZL50405GDC Datasheet - Page 98

• Manufacturer Part Number: ZL50405GDC
• Description: Managed5-Port 10/100 M Ethernet Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3.7
12.3.7.1
I²C Address 0BC, CPU Address:h600
Accessed by CPU and I²C (R/W)
12.3.7.2
I²C Address 0BD, CPU Address:h601
Accessed by CPU and I²C (R/W)
(Group 6 Address) MISC Group
Bits [3:1]
Bits [5:4]
Bits [7:6]
Bits [4:0]:
Bits [5]
Bits [6]
Bit [7]:
Bits [3:0]:
Bits [7:4]:
MII_OP0 – MII Register Option 0
MII_OP1 – MII Register Option 1
Transmit Priority (inclusive only)
Reserved
00 - No Filtering
01 - Exclusive Filtering (x<=RLOW or x>=RHIGH)
10 - Inclusive Filtering (RLOW<x<RHIGH)
11 - Invalid
Vendor specified link status register address (null value means don’t use it)
(Default 00). This is used if the Linkup bit position in the PHY is non-standard
Disable jabber detection. This is for HomePNA applications or any serial
operation slower than 10 Mbps.
0 = Enable
1 = Disable
Reserved
Half duplex flow control feature
0 = Half duplex flow control always enable
1 = Half duplex flow control by negotiation
Duplex bit location in vendor specified register
Speed bit location in vendor specified register
(Default 00)
Zarlink Semiconductor Inc.
ZL50405
98
Data Sheet