TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet
TFRA08C13-DB
Manufacturer Part Number
TFRA08C13-DB
Description
TFRA08C13 OCTAL T1/E1 Framer
Manufacturer
AGERE [Agere Systems]
Datasheet
1.TFRA08C13-DB.pdf
(188 pages)
- Current page: 1 of 188
- Download datasheet (3Mb)
October 2000
Features
T1/E1 Framer Features
Eight independent T1/E1 transmit and receive
framers.
Internal DS1 transmit clock synthesis—no external
oscillator necessary.
Comprehensive alarm reporting and performance
monitoring:
— Programmable automatic and on-demand alarm
Automatic facility data link:
— Automatic transmission of ESF performance
Common 2.048 Mbits/s, 4.096 Mbits/s, or
8.192 Mbits/s TDM highway.
Dual- or single-rail line-side I/O.
Supports one second polling interval for perfor-
mance monitoring.
IEEE * Std. 1149.1 JTAG boundary scan.
3.3 V low-power CMOS with 5 V tolerant inputs.
Available in 352-pin PBGA.
Supports T1 framing modes ESF, D4, SLC
T1DM DDS.
Supports G.704 basic and CRC-4 multiframe for-
mat E1 framing and procedures consistent with
G.706.
Supports unframed transmission format.
T1 signaling modes: transparent; ESF 2-state,
4-state, and 16-state; D4 2-state and 4-state;
SLC -96 2-state, 4-state, 9-state, and 16-state. E1
signaling modes: transparent and CAS.
Alarm reporting and performance monitoring per
AT&T, ANSI
Programmable, independent transmit and receive
system interfaces at a 2.048 MHz, 4.096 MHz, or
8.192 MHz data rate.
transmission.
report message.
†
, and ITU-T standards.
®
-96,
TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link Features
Microprocessor Interface
Applications
* IEEE is a registered trademark of The Institute of Electrical and
† ANSI is a registered trademark of American National Standards
‡ Intel is a registered trademark of Intel Corporation.
§ Motorola is a registered trademark of Motorola, Inc.
Electronics Engineers, Inc.
Institute, Inc.
HDLC or transparent mode.
Automatic transmission of the ESF performance
report messages (PRM).
Detection of the ESF PRM.
Detection of the ANSI ESF FDL bit-oriented codes.
64-byte FIFO in both transmit and receive direc-
tions.
Programmable FIFO full and empty level interrupt.
User-programmable microprocessor interface.
33 MHz read and write access.
12-bit address, 8-bit data interface.
Intel
Directly addressable internal registers.
Programmable interrupts.
DS3 and E3 port cards for narrowband DXCs.
Multiservice switches.
High density DS1 and E1 port cards.
Frame relay access devices.
Byte-synchronous SDH/SONET mapping.
SONET and SDH drop alignment.
IP and packet routers.
‡
or Motorola
§
style control interfaces.
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