TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 27

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
Pin Information
Table 2. Pin Descriptions (continued)
† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.
‡ Asserting this pin low will initially force RDY to a low state.
* I
u
indicates an internal pull-up, I
AE10
Pins
AD8
V26
H3
K1
K2
J1
J2
RDY_DTACK
INTERRUPT
Symbol
MPCK
(continued)
TRST
TDO
TMS
TCK
TDI
d
indicates an internal pull-down.
Type*
O
O
I
O
I
I
I
I
u
u
u
u
d
Interrupt. INTERRUPT is asserted high/low indicating an internal inter-
rupt condition/event has been generated. Interrupt events/conditions
are maskable through the control registers. This output can be wired-
OR or wired-AND to any other logic output (see Table 64Global Control
Register (GREG4) (004)).
Ready. In the Intel interface mode, this pin is asserted high to indicate
the completion of a read or write access; this pin is forced into a high-
impedance state while CS is high.
Data Transfer Acknowledge (Active-Low). In the Motorola interface
mode, DTACK is asserted low to indicate the completion of a read or
write access; DTACK is 1 otherwise.
Microprocessor Clock. Microprocessor clock used in the Intel mode to
generate the READY signal.
JTAG Data Output. Serial output data sampled on the falling edge of
TCK from the boundary-scan test circuitry.
JTAG Data Input. Serial input data sampled on the rising edge of TCK
for the boundary-scan test circuitry.
JTAG Clock Input. TCK provides the clock for the boundary-scan test
logic.
JTAG Mode Select (Active-High). The signal values received at TMS
are sampled on the rising edge of TCK and decoded by the boundary-
scan TAP controller to control boundary-scan test operations.
JTAG Reset Input (Active-Low). Assert this pin low to asynchronously
initialize/reset the boundary-scan test logic.
TFRA08C13 OCTAL T1/E1 Framer
Description
27