TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 100

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Concentration Highway Interface
Table 45. Summary of the TFRA08C13’s Concentration Highway Interface Parameters (continued)
100
RBYOFF6—RBYOFF0
TBYOFF6—TBYOFF0
RTSE31—RTSE0
TTSE31—TTSE0
ROFF2—ROFF0
TOFF2—TOFF0
THS31—THS0
RHS31—RHS0
STS0—STS2
Name
ASM
RCE
TCE
Transmitter Clock Edge (FRM_PR47 bit 6). TCE = 0 (or 1), TCHIDATA is clocked on
the falling (or rising) edge of CHICK.
Receiver Clock Edge (FRM_PR48 bit 6). RCE = 0 (or 1), RCHIDATA is latched on
the falling (or rising) edge of CHICK.
Transmit Time-Slot Enable 31—0 (FRM_PR49—FRM_PR52). These bits define
which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB
time slot. A 0 forces the CHI transmit highway time slot to be 3-stated.
Receive Time-Slot Enable 31—0 (FRM_PR53—FRM_PR56). These bits define
which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHDATAB
time slots. A 0 disables the time slot and transmits the programmable idle code of reg-
ister FRM_PR22 to the line interface.
Transmit Highway Select 31—0 (FRM_PR57—FRM_PR60). These bits define
which transmit CHI highway, TCHIDATA or TCHIDATAB, contains valid data for the
active time slot. A 0 enables TCHIDATA; a 1 enables the TCHIDATAB.
Receive Highway Select 31—0 (FRM_PR61—FRM_PR64). These bits define which
receive CHI highway, RCHIDATA or RCHIDATAB, contains valid data for the active
time slot. A 0 enables RCHIDATA; a 1 enables the RCHIDATAB.
Transmitter Bit Offset (FRM_PR46 bit 0—bit 2). These bits are used in conjunction
with the transmitter byte offset to define the beginning of the transmit frame. They
determine the offset relative to TCHIFS, for the first bit of transmit time slot 0. The off-
set is the number of CHICK cycles by which the first bit is delayed.
Receiver Bit Offset (FRM_PR46 bit 4—bit 6). These bits are used in conjunction
with the receiver byte offset to define the beginning of the receiver frame. They deter-
mine the offset relative to the RCHIFS, for the first bit of receive time slot 0. The offset
is the number of CHICK cycles by which the first bit is delayed.
Transmitter Byte Offset (FRM_PR47 bit 0—bit 5 and FRM_PR65 bit 0). These bits
determine the offset from the CHIFS to the beginning of the next frame on the trans-
mit highway. Note that in the ASM mode, a frame consists of 64 contiguous bytes;
whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets:
2.048 Mbits/s 0—31 bytes.
4.096 Mbits/s 0—63 bytes.
8.192 Mbits/s 0—127 bytes.
Receiver Byte Offset (FRM_PR48 bit 0—bit 5 and FRM_PR66 bit 0). These bits
determine the offset from CHIFS to the beginning of the receive CHI frame. Note that
in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes,
a frame contains 32 contiguous bytes. Allowable offsets:
2.048 Mbits/s 0—31 bytes.
4.096 Mbits/s 0—63 bytes.
8.192 Mbits/s 0—127 bytes.
Associated Signaling Mode (FRM_PR44 bit 2). When enabled, the associate sig-
naling mode configures the CHI to carry both payload data and its associated signal-
ing information. Enabling this mode must be in conjunction with the programming of
the CHI data rate to either 4.048 Mbits/s or 8.096 Mbits/s. Each time slot consists of
16 bits where 8 bits are data and the remaining 8 bits are signaling information.
Stuffed Time Slots (FRM_PR43 bit 0—bit 2). Valid only in T1 framing formats, these 3
bits define the location of the eight stuffed CHI (unused) time slots.
(continued)
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000