TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 175

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

Preliminary Data Sheet
October 2000
Lucent Technologies Inc.
Lucent Technologies Inc.
FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);
(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E))
Table 177. FDL Transmitter Status Register (FDL_SR1) (A0C; A2C; B0C; B2C; C0C; C2C; D0C; D2C)
* The count of FDL_SR1 bits 0—6 includes SF byte.
Table 178. FDL Receiver Status Register (FDL_SR2) (A0D; A2D; B0D; B2D; C0D; C2D; D0D; D2D)
* Immediately following an FDL reset, the value in bit 0—bit 6 of this status register is 0. After the initial read of the FDL receive FIFO, the value
Received FDL ANSI Bit Codes Status Register (FDL_SR3)
The 6-bit code extracted from the ANSI code 111111110X
Table 179. Receive ANSI FDL Status Register (FDL_SR3) (A0E; A2E; B0E; B2E; C0E; C2E; D0E; D2E)
Receive FDL FIFO Register (FDL_SR4)
This FIFO stores the received FDL data. Only valid FIFO bytes indicated in register FDL_SR2 may be read. Read-
ing nonvalid FIFO locations or reading the FIFO when it is empty will corrupt the FIFO pointer and will require an
FDL reset to restore proper FDL operation.
Table 180. FDL Receiver FIFO Register (FDL_SR4) (A07; A27; B07; B27; C07; C27; D07; D27)
in bit 0—bit 6 of this status register is the number of bytes, including SF byte, that may be read from the FIFO.
0—6
0—6
0—7
Bit
Bit
Bit
7
7
B7
0
FRD0—FRD7 FDL Receive Data. The user data received via the FDL block are read through this reg-
FRQS0—
FTQS0—
Symbol
Symbol
Symbol
FRQS6
FTQS6
FEOF
FTED
B6
0
FDL Transmit Queue Status. Bit 0—bit 6 indicate how many bytes can be added to the
transmit FIFO*. The bits are encoded in binary where bit 0 is the least significant bit.
FDL Transmitter Empty Dynamic. FTED = 1 indicates that the number of empty loca-
tions available in the transmit FIFO is greater than or equal to the value programmed in
the FTIL bits (FDL_PR3).
FDL Receive Queue Status. Bit 0—bit 6 indicate how many bytes are in the receive
FIFO, including the first status of Frame (SF) byte. The bits are encoded in binary where
bit 0 is the least significant bit*.
FDL End of Frame. When FEOF = 1, the receive queue status indicates the number of
bytes up to and including the first SF byte.
ister.
B5
X5
B4
X4
0
X
1
X
B3
X3
2
Description
Description
Description
X
3
X
4
X
5
TFRA08C13 OCTAL T1/E1 Framer
0 is stored in this register.
B2
X2
(continued)
B1
X1
B0
X0
175