TFRA08C13-DB AGERE [Agere Systems], TFRA08C13-DB Datasheet - Page 164

• Manufacturer Part Number: TFRA08C13-DB
• Description: TFRA08C13 OCTAL T1/E1 Framer
• Manufacturer: AGERE [Agere Systems]

TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture
CHI Transmit Control Register (FRM_PR65)
The default value of this register is 00 (hex).
Table 158. CHI Transmit Control Register (FRM_PR65) (YA1)
CHI Receive Control Register (FRM_PR66)
The default value of this register is 00 (hex).
Table 159. CHI Receive Control Register (FRM_PR66) (YA2)
164
2—7
2—7
Bit
Bit
0
1
0
1
TBYOFF6
RBYOFF6
TCHIDTS
RCHIDTS
Symbol
Symbol
—
—
Transmit CHI 64-Byte Offset. A 1 enables a 64-byte offset from CHIFS to the beginning
of the next transmit CHI frame on TCHIDATA. A 0 enables a 0-byte offset (if bit 0—bit 5
of FRM_PR47 = 0). Combing bit 0—bit 5 of FRM_PR47 with this bit allows programming
the byte offset from 0—127.
Transmit CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot
mode. In this mode, the CHI clock runs at twice the rate of TCHIDATA.
Reserved. Write to 0.
Receive CHI 64-Byte Offset. A 1 enables a 64-byte offset from CHIFS to the beginning of
the next receive CHI frame on RCHIDATA. A 0 enables a 0-byte offset (if bit 0—
bit 5 of FRM_PR48 = 0). Combing bit 0—bit 5 of FRM_PR48 with this bit allows program-
ming the byte offset from 0—127.
Receive CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot
mode. In this mode, the CHI clock runs at twice the rate of RCHIDATA.
Reserved. Write to 0.
(continued)
Description
Description
Preliminary Data Sheet
Lucent Technologies Inc.
Lucent Technologies Inc.
October 2000