AM41DL3208G AMD [Advanced Micro Devices], AM41DL3208G Datasheet
AM41DL3208G
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AM41DL3208G Summary of contents
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... Am41DL3208G Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
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... PRELIMINARY Am41DL3208G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features I Power supply voltage of 2.7 to 3.3 volt I High performance — Access time as fast Package — ...
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... Bank Twenty-four 64 Kbyte/32 Kword Bank Eight 64 Kbyte/32 Kword Am41DL3208G Features TM The SecSi (Secured Silicon) Sector is an 256 byte extra sector capable of being permanently locked by AMD or cus- tomers. The SecSi Indicator Bit (DQ7) is permanently set the part is factory locked, and set cus- tomer lockable ...
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... Flash Erase and Program Operations .................................... 47 Figure 18. Program Operation Timings.......................................... 48 Figure 19. Accelerated Program Timing Diagram.......................... 48 Figure 20. Chip/Sector Erase Operation Timings .......................... 49 Figure 21. Back-to-back Read/Write Cycle Timings ...................... 50 Figure 22. Data# Polling Timings (During Embedded Algorithms). 50 Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 51 Figure 24. DQ2 vs. DQ6................................................................. 51 Am41DL3208G vs. Frequency ............................................ 41 3 ...
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... Flash Latchup Characteristics Package Pin Capacitance . . . . . . . . . . . . . . . . . . 61 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 61 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 62 Figure 33. CE1#s Controlled Data Retention Mode....................... 62 Figure 34. CE2s Controlled Data Retention Mode......................... 62 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 63 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 64 Revision A (January 3, 2002) ................................................. 64 Am41DL3208G February 13, 2002 ...
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... CIOs February 13, 2002 Am41DL3208G Flash Memory RY/BY Bit Flash Memory DQ15/A-1 to DQ0 V s CCQ SS SSQ 8 M Bit DQ15/A-1 to DQ0 Static RAM Am41DL3208G SRAM DQ15/A-1 to DQ0 5 ...
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... A20–A0 RESET# STATE CONTROL WE# & CE# COMMAND CIOf REGISTER WP#/ACC DQ15–DQ0 A20– Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address Am41DL3208G OE# CIOf DQ15–DQ0 OE# CIOf February 13, 2002 ...
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... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am41DL3208G Flash only A10 NC SRAM only B10 NC Shared F10 ...
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... SRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 19 A18–A0 A-1, A20–A19 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf CIOs Am41DL3208G DQ15–DQ0 RY/BY# February 13, 2002 ...
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... Am29DL320G 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM Valid Combinations Order Number Am41DL3208GT70I Am41DL3208GB70I T Am41DL3208GT85I Am41DL3208GB85I February 13, 2002 TAPE AND REEL inches ...
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... The state machine outputs dictate the function of the device. Tables 1 through 3 list the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail. Am41DL3208G February 13, 2002 ...
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... Don’t Care SRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL3208G ; SRAM Word Mode, CIOs = WP#/ACC DQ7– DQ15– (Note 4) DQ0 X H L/H D OUT ...
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... 9.0 ± 0 Don’t Care SRAM Address Address In Data In and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL3208G ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 X H L/H ...
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... 9.0 ± 0 Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL3208G ; SRAM Word Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 4) DQ0 X H ...
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... Don’t Care SRAM Address Address In (for Flash Byte Mode, DQ15 = A-1 and CE2s = V at the same time. IH the boot sectors protection will be removed. IH Am41DL3208G ; SRAM Byte Mode, CIOs = UB#s WP#/ACC DQ7– RESET# (Note 3) (Note 4) DQ0 ...
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... Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Am41DL3208G on this pin, the device auto- HH for operations other than accelerated pro- and I in the DC Characteristics table ...
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... The output pins are placed in the high impedance state. Table 5. Device Bank Division Bank Megabits Bank Bank Bank Bank Am41DL3208G ± 0.3 V, the de RESET# is CC4 ± 0.3 V, the standby cur- SS (not during Embed- READY after output from the device is IH ...
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... Am41DL3208G (x16) Address Range 000000h–07FFFh 008000h–0FFFFh 010000h–17FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h– ...
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... A20:A0 in word mode (BYTE#=V IL Top Boot SecSi Sector Addresses Sector Address Sector Size A20–A12 (Bytes/Words) 111111xxx 256/128 Am41DL3208G (x16) Address Range 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h– ...
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... Am41DL3208G (x8) (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h– ...
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... A20:A0 in word mode (BYTE#=V IL Bottom Boot SecSi Sector Addresses Sector Address Sector Size A20–A12 (Bytes/Words) 000000xxx 256/128 Am41DL3208G (x16) Address Range 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h– ...
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... Kbytes That is, sector protection or unprotection for these two sectors depends on whether they were last protected 8 Kbytes or unprotected using the method described in “Sec- 8 Kbytes tor/Sector Block Protection and Unprotection”. Am41DL3208G Sector/ A20–A12 Sector Block Size 111111100 8 Kbytes 111111101 8 Kbytes ...
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... Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation Am41DL3208G START RESET (Note 1) Perform Erase or Program Operations RESET ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am41DL3208G START PLSCNT = 1 RESET Wait 1 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one Am41DL3208G This the device does not ac- LKO CC is greater than V ...
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... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am41DL3208G Description 25 ...
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... Erase Block Region 2 Information 0000h 0001h 0000h 0000h Erase Block Region 3 Information 0000h 0000h 0000h 0000h Erase Block Region 4 Information 0000h 0000h Am41DL3208G Description pin present) PP pin present µs N µ s (00h = not supported (00h = not supported) ...
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... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 0085h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 0095h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 000Xh 02h = Bottom Boot Device, 03h = Top Boot Device Am41DL3208G Description 27 ...
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... A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h unprotected. (Refer to Ta- bles 6–8 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Am41DL3208G February 13, 2002 ...
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... Figure 3 illustrates the algorithm for the program oper- a tio Fla Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Am41DL3208G any operation HH 29 ...
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... When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- Am41DL3208G February 13, 2002 ...
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... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Tables 15 and 16 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am41DL3208G START Embedded Erase algorithm in progress Yes 31 ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am41DL3208G Fourth Fifth Sixth Data Addr ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am41DL3208G Fourth Fifth Sixth Addr Data ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am41DL3208G Yes No Yes Yes No ...
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... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm Am41DL3208G No Yes Yes No Yes ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 17 shows the status of DQ3 relative to the other status bits. Am41DL3208G February 13, 2002 ...
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... The device outputs array data if the system addresses a non-busy bank. February 13, 2002 Table 17. Write Operation Status DQ7 DQ5 DQ6 (Note 2) (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am41DL3208G DQ2 DQ3 RY/BY# (Note 2) 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... Operating ranges define those limits between which the func- tionality of the device is guaranteed –2 +2 +0.5 V 2.0 V Figure 8. Maximum Positive Am41DL3208G ) . . . . . . . . .–40°C to +85° Overshoot Waveform February 13, 2002 ...
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... OE pin 4.0 mA min I = –2.0 mA min I = –100 µ min Am41DL3208G Min Typ Max Unit ±1.0 µA 35 µA ±1.0 µA 35 µ 0.2 5 µA 0.2 5 µ ...
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... IH IL inputs = CE1#s ≥ V – 0.2 V, CE2 ≥ V – 0.2 V (CE1#s controlled) or CE2 ≤ 0.2 V (CE2s controlled), CIOs = Other input = Am41DL3208G + 30 ns. Typical sleep mode current is ACC Min Typ Max Unit –1.0 1.0 µA –1.0 1.0 µ ...
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... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note °C February 13, 2002 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am41DL3208G 3000 3500 4000 3 ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am41DL3208G 70 Unit 1 TTL gate 0.0–3 ...
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... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR CE#f CE1#s CE2s Figure 13. Timing Diagram for Alternating Between SRAM to Flash February 13, 2002 Test Setup — t CCR t CCR Am41DL3208G All Speeds Unit Min CCR t CCR 43 ...
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... Test Setup CE# Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operation Timings Am41DL3208G Speed Options 70 85 Min 70 85 Max Max Max 30 40 Max 16 Max 16 Min 0 ...
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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings Am41DL3208G All Speeds Unit 20 µs 500 ns 500 µ ...
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... Data Output (DQ0–DQ7) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am41DL3208G Speed Options Unit Data Output (DQ0–DQ7) Address Input Data Output (DQ0–DQ14) February 13, 2002 ...
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... Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. February 13, 2002 CE#f Low During Toggle Bit Read Toggle and Data# Polling Byte Word Am41DL3208G Speed Options Unit 70 85 Min Min ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am41DL3208G Read Status Data (last two cycles WHWH1 Status D OUT VHH February 13, 2002 ...
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... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings February 13, 2002 SADD 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am41DL3208G Read Status Data WHWH2 In Complete Progress ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am41DL3208G Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z True Valid Data High Z Valid Data True February 13, 2002 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am41DL3208G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 51 ...
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... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector/Sector Block Unprotect Min Min Min Min Program or Erase Command Sequence t RSP Timing Diagram Am41DL3208G All Speed Options Unit 500 ns 250 ns µs 4 µ VIDR ...
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... For sector protect For sector unprotect Figure 26. Sector/Sector Block Protect and Unprotect February 13, 2002 Valid* Valid* Verify 60h 40h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Timing Diagram Am41DL3208G Valid* Status 53 ...
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... See the “Flash Erase And Programming Performance” section for more information Min Min Min Min Min Min Min Min Min Min Min Min Byte Typ Word Typ Typ Typ Am41DL3208G Speed Options Unit ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am41DL3208G PA DQ7# D OUT 55 ...
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... Figure 28. SRAM Read Cycle—Address Controlled Min Max Max Max Max Min Min Min Max Max Max Min UB#s and/or LB Am41DL3208G Speed Options Unit ...
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... February 13, 2002 CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ Am41DL3208G BHZ t OHZ 57 ...
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... (See Note (See Note 4) High applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL3208G Speed Options Unit ...
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... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL3208G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... Note 4) WP (See Note High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when Am41DL3208G t (See Note Data Valid High-Z is measured from the beginning of write ...
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... V, one pin at a time. CC Test Setup OUT Test Conditions Am41DL3208G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... CS1#s ≥ V – 0.2 V (Note 3.0 V, CE1#s ≥ – 0 (Note 1) See data retention waveforms Data Retention Mode t SDR ≥ CE1 0 Data Retention Mode t SDR CE2s < 0.2 V Am41DL3208G Min Typ Max Unit 1.5 3.3 V 1.0 15 µA (Note ...
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... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm February 13, 2002 Am41DL3208G 63 ...
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... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies Am41DL3208G February 13, 2002 ...