AM41DL3224GB30IS AMD [Advanced Micro Devices], AM41DL3224GB30IS Datasheet - Page 59

• Manufacturer Part Number: AM41DL3224GB30IS
• Description: 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
• Manufacturer: AMD [Advanced Micro Devices]

AC CHARACTERISTICS
SRAM Write Cycle
Notes:
1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
3. t
4. t
5. A write occurs during the overlap (t
58
Parameter
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Symbol
t
is measured from the address valid to the beginning of write.
t
t
t
t
t
t
t
t
WHZ
t
t
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
WC
WR
DW
OW
AW
BW
WP
Cw
AS
DH
Address
CS1#s
CS2s
UB#s, LB#s
WE#
Data In
Data Out
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Figure 30. SRAM Write Cycle—WE# Control
WP
Data Undefined
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
(See Note 4)
P R E L I M I N A R Y
t
AS
Am41DL32x4G
t
BW
(See Note 2)
(See Note 2)
WR
t
AW
applied in case a write ends as CE1#s or WE# going high.
(See Note 5)
t
WC
t
t
t
CW
BW
CW
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
min
t
WP
t
DW
Data Valid
WP
70
70
60
60
60
50
20
30
is measured from the beginning of write
0
t
Speed Options
WR
t
DH
t
(See Note 3)
OW
0
0
0
5
High-Z
85
85
70
70
70
60
25
35
November 12, 2001
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns