M36L0R7050L1 STMICROELECTRONICS [STMicroelectronics], M36L0R7050L1 Datasheet

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M36L0R7050L1

Manufacturer Part Number
M36L0R7050L1
Description
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Feature summary
Flash memory
June 2006
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Multi-Chip Package
– 1 die of 128 Mbit (8Mb x16, Mux I/O
– 1 die of 32 or 64Mbit Mux I/O, Burst
Supply voltage
– V
– V
Electronic signature
– Manufacturer Code: 20h
– Device Codes (Top Flash Configuration):
– Device Codes (Bottom Flash Configuration)
ECOPACK® package
Multiplexed address/data
Synchronous / asynchronous read
– Synchronous Burst Read mode: 66MHz
– Random Access: 85ns
Synchronous burst read suspend
programming time
– 10µs typical Word program time using
Memory organization
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
100,000 program/erase cycles per block
memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
Multiple Bank, Multi-level, Burst) Flash
Memory
Pseudo SRAM
M36L0R7060U1: 882Eh,
M36L0R7050U1: 882Eh
M36L0R7060L1: 882Fh
M36L0R7050L1: 882Fh
Buffer Enhanced Factory Program
command
DDF
PPF
= 9V for fast program
= V
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash
DDP
= V
DDQF
= 1.7 to 1.95V
M36L0R7060U1 M36L0R7060L1
M36L0R7050U1 M36L0R7050L1
Rev 1
PSRAM
Dual operations
– program/erase in one Bank while read in
– No delay between Read and Write
– All blocks locked at power-up
– Any combination of blocks can be locked
– WP
– Absolute Write Protection with V
Common Flash Interface (CFI)
Access time: 70ns
Synchronous modes:
– Synchronous Write: continuous burst
– Synchronous Read: continuous burst or
– Maximum Clock Frequency: 83MHz
Low power consumption
Low power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Block locking
others
operations
with zero latency
fixed length: 4, 8 or 16 Words for 32 Mbit
devices or 4, 8,16 or 32 Words for 64 Mbit
devices
Refresh
F
for Block Lock-Down
TFBGA88 (ZAM)
8 x 10mm
FBGA
Preliminary Data
PPF
www.st.com
= V
1/22
SS
1

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M36L0R7050L1 Summary of contents

Page 1

... June 2006 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. M36L0R7060U1 M36L0R7060L1 M36L0R7050U1 M36L0R7050L1 Dual operations – program/erase in one Bank while read in others – No delay between Read and Write ...

Page 2

... Flash memory Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDF 2.18 V PSRAM Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CCP 2.19 V Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDQF 2.20 V Flash memory Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . 13 PPF 2.21 V Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SS 2.22 V Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SSQ 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents 3/22 ...

Page 4

... Operating modes - Standard Asynchronous operation Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Device capacitance Table 6. Stacked TFBGA88 8 × 10mm - 8 × 10 active ball array, 0.8mm pitch, package data . . . . 19 Table 7. Part numbering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 ...

Page 5

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. TFBGA connections (top view through package Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package outline ...

Page 6

... Summary description 1 Summary description The M36L0R7060U1, M36L0R7060L1, M36L0R7050U1 and M36L0R7050L1 combine two memory devices in a Multi-Chip Package: a 128-Mbit, Multiple Bank Flash memory, the M58LR128G(U/ Mbit PseudoSRAM, the M69KM048AA or M69KM096AA, respectively. The purpose of this document is to describe how the two memory components operate with respect to each other ...

Page 7

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Figure 1. Logic diagram V V DDQF PPF V V DDF 23 A16-A22 M36L0R7060U1 WP F M36L0R7060L1 L M36L0R7050U1 K M36L0R7050L1 Summary description DDP 16 ADQ0-ADQ15 WAIT Ai12016 7/22 ...

Page 8

... Flash memory and the PSRAM 2. A21-A22 (if the MCP contains a 32Mb PSRAM) or A22 (if the MCP contains a 64Mb PSRAM) are Address Input(s) for the Flash memory component only. 8/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Address Inputs Flash memory and PSRAM common Data Input/Outputs, Address Inputs or Command Inputs ...

Page 9

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Figure 2. TFBGA connections (top view through package A18 A19 DDF A17 NC V PPF ...

Page 10

... The Wait output is common to the Flash memory and PSRAM components. For details of how the WAIT signal behaves, please refer to the datasheets of the respective memory components: M69KM048AA or M69KM096AA for the PSRAM and M58LRxxxGUL for the Flash memory 10/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 and Table 1: Signal names, for a brief overview of the signals ...

Page 11

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 2.6 Flash memory Chip Enable (E The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable mode. When Chip Enable impedance and the power consumption is reduced to the stand-by level. ...

Page 12

... Flash memory operations (Read, Program and Erase). 2.18 V PSRAM Supply Voltage CCP The V Supply Voltage is the core supply voltage. CCP 12/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 ) P , the Output Enable enables the Bus Read operations of the controls the Bus Write operation of the memory. When asserted (V ...

Page 13

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 2.19 V Supply Voltage DDQF V provides the power supply to the I/O pins and enables all Outputs to be powered DDQF independently of V 2.20 V Flash memory Program Supply Voltage PPF V is both a control input and a power supply pin. The two functions are selected by the PPF voltage range applied to the pin ...

Page 14

... Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram (1) A16-A20 (2) or A16-A21 1. Address Inputs corresponding to the M36L0R7050U1 and M36L0R7050L1 devices. 2. Address Inputs corresponding to the M36L0R7060U1 and M36L0R7060L1 devices. 14/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 DDQF ...

Page 15

... Operating mode available in the M36L0R7060U1 and M36L0R7060L1 only (see M69KM096AA datasheet). 5. BCR and RCR only the PSRAM of the M36L0R7050U1 and M36L0R7050L1, A19 is used to select between the BCR and the RCR whereas in the PSRAM of the M36L0R7060U1 and M36L0R7060L1 both A18 and A19 are used to select the BCR, the RCR or the DIDR ...

Page 16

... Input or Output Voltage Core and Input/Output Supply DDF DDQF V Voltages CCP V Flash Program Voltage PPF I Output Short Circuit Current O t Time for V VPPFH 16/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Parameter at V PPF PPFH Value Min Max –25 85 –25 85 –55 125 –0.2 2.45 –0.2 2.45 –0.2 10 ...

Page 17

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and AC measurement operating conditions in their circuit match the operating conditions when relying on the quoted parameters ...

Page 18

... Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58LRxxxGUL and M69KM048AA or M69KM096AA datasheets for further DC and AC characteristics values and illustrations. 18/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 V V DDF DDQF DEVICE UNDER TEST 0.1µF 0.1µF C includes JIG capacitance ...

Page 19

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 6 Package mechanical Figure 6. TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package outline 1. Drawing is not to scale. Table 6. Stacked TFBGA88 8 × 10mm - 8 × 10 active ball array, 0.8mm pitch, package data Symbol Typ 0.850 b 0.350 D 8.000 D1 5 ...

Page 20

... Devices are shipped from the factory with the memory content bits, in valid blocks, erased to ’1’. For further information on any aspect of this device, please contact your nearest ST Sales Office. 20/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 = 1.7V to 1.95V DDQF M36 ZAM F ...

Page 21

... M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 8 Revision history Table 8. Document revision history Date 08-Jun-2006 Revision 1 Initial release. Revision history Changes 21/22 ...

Page 22

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 22/22 M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...

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