AM49DL6408H55FS SPANSION [SPANSION], AM49DL6408H55FS Datasheet - Page 52

• Manufacturer Part Number: AM49DL6408H55FS
• Description: 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit)
• Manufacturer: SPANSION [SPANSION]

PSEUDO SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
50
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Parameter
Symbol
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
t
t
t
t
t
t
t
t
t
WHZ
t
t
WC
AW
BW
WP
WR
DW
OW
Cw
DH
AS
Address
CE1#s
CE2s
WE#
Data In
Data Out
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Figure 29. Pseudo SRAM Write Cycle—WE# Control
WP
A D V A N C E
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
Data Undefined
High-Z
(See Note 3)
t
AS
Am49DL6408H
I N F O R M A T I O N
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
t
WR
WHZ
(See Note 1)
(See Note 1)
applied in case a write ends as CE1#s or WE# going high.
t
AW
t
(See Note 4)
WC
t
t
CW
CW
t
WP
t
55
55
45
45
45
45
DW
Data Valid
WP
is measured from the beginning of write
Speed
25
40
0
0
0
0
5
t
DH
t
t
WR
OW
70, 85
70
55
55
55
55
High-Z
March 12, 2004
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns