AM49PDL127AH61IS SPANSION [SPANSION], AM49PDL127AH61IS Datasheet
AM49PDL127AH61IS
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AM49PDL127AH61IS Summary of contents
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Am49PDL129AH Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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ADVANCE INFORMATION Am49PDL127AH/Am49PDL129AH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit ( 16-Bit) CMOS Pseudo Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power ...
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PSRAM FEATURES Power dissipation — Operating maximum — Standby: 70 µA maximum — Deep power-down standby: 5 µA CE1s# and CE2ps Chip Select Power down features using CE1s# and CE2ps Data ...
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GENERAL DESCRIPTION (PDL129) The Am29PDL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device ...
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GENERAL DESCRIPTION (PDL127) The Am29PDL127H is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. This device ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 7 MCP Block Diagram . . ...
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Between Pseudo SRAM and Flash................................................. 59 Flash AC Characteristics . . . . . . . . . . . . . . . . . . . 60 Read-Only Operations – Am29PDL127H ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Range: Speed Option V = 2.7–3 Max Access Time, ns Page Access Time, ns CE#f1 Access, ns OE# Access, ns MCP BLOCK DIAGRAM (A22) ...
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CONNECTION DIAGRAM–PDL129 LB UB A18 A17 G1 ...
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CONNECTION DIAGRAM–PDL127 LB UB A18 A17 G1 ...
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LOOK AHEAD PINOUT VSSds CLK ADV WP ...
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PIN DESCRIPTION A19– Address Inputs (Common) A21-A20 = 2 Address Inputs (Flash) A22 = Address Input (PDL127 only) (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash) ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49PDL12 AMD DEVICE NUMBER/DESCRIPTION Am49PDL127AH/Am49PDL129AH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8 M ...
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CE#f2 Operation CE#f1 (PDL129 (Notes 1, 2) Active only) (Note 7) Read from L (H) H (L) Active Flash (Note 8) (Note 7) Write to Active L (H) H (L) Flash (Note 8) ...
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Refer to the Flash AC Characteristics table for timing specifications and to Figure 13 for the timing diagram the DC Characteristics table represents the ac- CC1 tive current specification for reading ...
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Characteristics section contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended ...
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Table 5. SecSi Sector Addresses Sector Size Am29PDL127H/ 128 words Am29PDL129H Table 6. Am29PDL127H Sector Architecture Bank Sector Factory-Locked Area ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 ...
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Table 6. Am29PDL127H Sector Architecture (Continued) SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 ...
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Table 7. Am29PDL129H Sector Architecture Bank Sector CE#f1 SA1-0 0 SA1-1 0 SA1-2 0 SA1-3 0 SA1-4 0 SA1-5 0 SA1-6 0 SA1-7 0 SA1-8 0 SA1-9 0 SA1-10 0 SA1-11 0 SA1-12 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) Bank Sector CE#f1 December 18, 2003 Sector Address CE#f2 (A21-A12) Am49PDL127AH/Am49PDL129AH Sector Size Address Range (x16) ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA1-38 0 SA1-39 0 SA1-40 0 SA1-41 0 SA1-42 0 SA1-43 0 SA1-44 0 SA1-45 0 SA1-46 0 SA1-47 0 SA1-48 0 SA1-49 0 SA1-50 0 SA1-51 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA1-78 0 SA1-79 0 SA1-80 0 SA1-81 0 SA1-82 0 SA1-83 0 SA1-84 0 SA1-85 0 SA1-86 0 SA1-87 0 SA1-88 0 SA1-89 0 SA1-90 0 SA1-91 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA1-96 0 SA1-97 0 SA1-98 0 SA1-99 0 SA1-100 0 SA1-101 0 SA1-102 0 SA1-103 0 SA1-104 0 SA1-105 0 SA1-106 0 SA1-107 0 SA1-108 0 SA1-109 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA2-0 1 SA2-1 1 SA2-2 1 SA2-3 1 SA2-4 1 SA2-5 1 SA2-6 1 SA2-7 1 SA2-8 1 SA2-9 1 SA2-10 1 SA2-11 1 SA2-12 1 SA2-13 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA2-39 1 SA2-40 1 SA2-41 1 SA2-42 1 SA2-43 1 SA2-44 1 SA2-45 1 SA2-46 1 SA2-47 1 SA2-48 1 SA2-49 1 SA2-50 1 SA2-51 1 SA2-52 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA2-79 1 SA2-80 1 SA2-81 1 SA2-82 1 SA2-83 1 SA2-84 1 SA2-85 1 SA2-86 1 SA2-87 1 SA2-88 1 SA2-89 1 SA2-90 1 SA2-91 1 SA2-92 ...
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Table 7. Am29PDL129H Sector Architecture (Continued) SA2-119 1 SA2-120 1 SA2-121 1 SA2-122 1 SA2-123 1 SA2-124 1 SA2-125 1 SA2-126 1 SA2-127 1 SA2-128 1 SA2-129 1 SA2-130 1 SA2-131 1 SA2-132 ...
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SA203-SA206 110001XXXXX SA207-SA210 110010XXXXX SA211-SA214 110011XXXXX SA215-SA218 110100XXXXX SA219-SA222 110101XXXXX SA223-SA226 110110XXXXX SA227-SA230 110111XXXXX SA231-SA234 111000XXXXX SA235-SA238 111001XXXXX SA239-SA242 111010XXXXX SA243-SA246 111011XXXXX SA247-SA250 111100XXXXX SA251-SA254 111101XXXXX SA255-SA258 111110XXXXX SA259 11111100XXX SA260 11111101XXX SA261 ...
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SA2-83 - SA2-86 10011XXXXX SA2-87 - SA2-90 10100XXXXX SA2-91 - SA2-94 10101XXXXX SA2-95 - SA2-98 10110XXXXX SA2-99 - SA2-102 10111XXXXX SA2-103 - SA2-106 11000XXXXX SA2-107 - SA2-110 11001XXXXX SA2-111 - SA2-114 11010XXXXX SECTOR ...
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Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is “0”. Each DYB is individually modifiable through the DYB ...
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The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/ PPB lock verify command to the device. Persistent Sector Protection Mode Locking Bit ...
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Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit ...
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START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin During ...
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Increment PLSCNT No PLSCNT = 25? Yes Device Failed Figure 3. SecSi Sector Protection Algorithm START TM SecSi Sector Entry Write ...
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Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region com- mand sequence to return to reading and writing the remainder of the array. The ...
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17h 0000h 18h 0000h 19h 0000h 1Ah 0000h Addresses Data 1Bh 0027h 1Ch 0036h 1Dh 0000h 1Eh 0000h 1Fh 0004h 20h 0000h 21h 0009h 22h 0000h 23h 0005h 24h 0000h 25h 0004h 26h ...
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Table 15. Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 000Ch 46h 0002h 47h 0001h 48h 0001h 49h 0007h 4Ah 00E7h 4Bh 0000h 4Ch ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 16 defines the valid register command sequences. Writing incorrect address and data val- ...
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Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector ...
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START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 16 for program command sequence. Figure 4. ...
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termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the ...
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the password when programming. There are no pro- visions for entering the 2-cycle unlock cycle, the pass- word program command, and all the password data. There is no special addressing order required ...
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Password Unlock Command The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become ac- cessible for ...
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Command Definitions Tables Table 16. Memory Array Command Definitions Command (Notes) Read (5) 1 Reset (6) 1 Manufacturer ID 4 Device ID (10) 6 Autoselect SecSi Sector Factory 4 (Note 7) Protect (8) ...
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Table 17. Sector Protection Command Definitions Command (Notes) Addr Data Addr Data Addr Data Reset 1 XXX F0 SecSi Sector Entry 3 555 AA 2AA 55 SecSi Sector Exit 4 555 AA 2AA ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsections describe the function ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied ...
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CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I A9, OE#, RESET# Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current LO V Active ...
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pSRAM DC & OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current Operating Current CC1 V Output Low Voltage OL V Output High Voltage ...
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TEST CONDITIONS Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 10. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V ...
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pSRAM AC CHARACTERISTICS CE#1ps Timing Parameter JEDEC Std Description — t CE#1ps Recover Time CCR CE#f CE1#s CE2s Figure 12. Timing Diagram for Alternating ...
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FLASH AC CHARACTERISTICS Read-Only Operations – Am29PDL127H Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to ...
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FLASH AC CHARACTERISTICS Addresses CE# CE#f2 RH (PDL 129 only) OE# WE# Outputs RESET# RY/BY Addresses A2-A0 Data CE CE#f2 (PDL129 only) OE# Figure 14. Page Read ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f1 or CE#f2 t (PDL129 only) GHWL OE# WE Data RY/BY VCS Notes: 1. ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE#f1 or CE#f2 t GHWL (PDL129 only Data 55h RY/BY# t VCS ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f1 or CE#f2 (PDL129 only) OE WE# t WPH t DS Data WE# Controlled Write Cycle Figure 19. Back-to-back Read/Write Cycle ...
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FLASH AC CHARACTERISTICS Addresses CE#f1 or CE#f2 (PDL129 only) t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 1 µs CE#f1 or CE#f1(PDL129 only) WE# OE# 1. For sector protect ...
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FLASH AC CHARACTERISTICS Alternate CE#f1 Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE# CE#f2 (PDL129 only) Data t RH RESET# RY/BY# Notes: 1. Figure indicates last ...
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PSEUDO SRAM AC CHARACTERISTICS Power Up Time When powering up the SRAM, maintain V Read Cycle Parameter Description Symbol t Read Cycle Time RC t Address Access Time Chip ...
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PSEUDO SRAM AC CHARACTERISTICS Read Cycle Address CE#1s CE2s OE# Data Out High-Z Notes and t are defined as the time at which the outputs ...
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PSEUDO SRAM AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Chip Enable to End of Write Cw t Address Setup Time AS t Address Valid to End of ...
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PSEUDO SRAM AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. CE1#s controlled measured from CE1#s going low to the end of write ...
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PSEUDO SRAM AC CHARACTERISTICS Address CE1#s CE2s UB#s, LB#s WE# Data In Data Out Notes: 1. UB#s and LB#s controlled measured from CE1#s going low to the end of write. ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following ...
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PHYSICAL DIMENSIONS TLA073—73-Ball Fine-Pitch Grid Array 0.15 C (2X) PIN A1 10 CORNER INDEX MARK TOP VIEW SIDE VIEW 6 b 73X 0. ...
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REVISION SUMMARY Revision A (August 7, 2003) Initial release. Revision A+1 (December 18, 2003) TM SecSi (Secured Silicon) Sector Flash Memory Region Customer-Lockable Area: Added sector protection fig- ure and changed figure reference ...