AM49PDL127AH61IS SPANSION [SPANSION], AM49PDL127AH61IS Datasheet - Page 75
AM49PDL127AH61IS
Manufacturer Part Number
AM49PDL127AH61IS
Description
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 16 Mbit (1 M x 16-Bit) CMOS Pseudo Static RAM
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM49PDL127AH61IS.pdf
(82 pages)
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PSEUDO SRAM AC CHARACTERISTICS
Power Up Time
When powering up the SRAM, maintain V
Read Cycle
Notes:
1. CE1#s = OE# = V
2. Do not access device with cycle timing shorter than t
December 18, 2003
Parameter
t
CO1
t
Symbol
LZ1
t
t
t
t
t
t
t
t
t
t
BHZ
OHZ
BLZ
OLZ
OH
RC
AA
OE
BA
HZ
, t
, t
CO2
LZ2
Address
Data Out
Description
Read Cycle Time
Address Access Time
Chip Enable to Output
Output Enable Access Time
LB#s, UB#s to Access Time
Chip Enable (CE1#s Low and CE2s High) to Low-Z
Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#s, LB#s Disable to High-Z Output
Output Disable to High-Z Output
Output Data Hold from Address Change
IL
, CE2s = WE# = V
Figure 26. Pseudo SRAM Read Cycle—Address Controlled
Previous Data Valid
A D V A N C E
IH
Am49PDL127AH/Am49PDL129AH
, UB#s and/or LB#s = V
CC
s for 100 µs minimum with CE#1s at V
t
OH
RC
for continuous periods < 10 µs.
I N F O R M A T I O N
t
AA
IL
t
RC
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
61
55
55
55
30
55
IH
Data Valid
.
Speed
25
25
25
10
5
5
5
70
70
70
70
35
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
73
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