GS8640ZV36GT-300I GSI [GSI Technology], GS8640ZV36GT-300I Datasheet
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GS8640ZV36GT-300I
Related parts for GS8640ZV36GT-300I
GS8640ZV36GT-300I Summary of contents
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... The GS8640ZV18/36T is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/ single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. ...
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DDQ ...
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DQP DDQ ...
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TQFP Pin Descriptions Symbol Type ...
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... GS8640ZV18/36 NBT SRAM Functional Block Diagram Rev: 1.00 9/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8640ZV18/36T-300/250/200/167 Amps Sense Drivers Write 5/23 Product Preview © 2004, GSI Technology ...
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... A B cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
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Pipeline and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.00 9/2004 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.00 9/2004 Specifications cited are subject to change without notice. For latest documentation see ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
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Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...
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Logic Levels Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Operating Currents Parameter Test Conditions (x32/ x36) Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open (x18) Standby ZZ ≥ V – 0.2 V — DD Current Device Deselected; Deselect All other inputs — ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
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Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.00 9/2004 Specifications cited ...
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Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...
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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
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... GS8640ZV18GT-167 GS8640ZV36GT-300 GS8640ZV36GT-250 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640ZV36T-167IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... GS8640ZV36GT-167 GS8640ZV18GT-300I GS8640ZV18GT-250I GS8640ZV18GT-200I GS8640ZV18GT-167I GS8640ZV36GT-300I GS8640ZV36GT-250I GS8640ZV36GT-200I GS8640ZV36GT-167I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640ZV36T-167IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
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... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 8640ZVxx_r1 Rev: 1.00 9/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8640ZV18/36T-300/250/200/167 Page;Revisions;Reason • Creation of new datasheet 23/23 Product Preview © 2004, GSI Technology ...