GS8644V72C-250I GSI [GSI Technology], GS8644V72C-250I Datasheet - Page 12

• Manufacturer Part Number: GS8644V72C-250I
• Description: 4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There are pull-up devices onthe ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.03 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
FLXDrive Output Impedance Control
Single/Dual Cycle Deselect Control
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
12/40
SCD
LBO
ZQ
ZZ
FT
GS8644V18(B/E)/GS8644V36(B/E)/GS8644V72(C)
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
1st address
3rd address
4th address
H or NC
H or NC
H or NC
L or NC
State
H
H
L
L
L
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
High Drive (Low Impedance)
Low Drive (High Impedance)
Single Cycle Deselect
Dual Cycle Deselect
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
Product Preview
© 2003, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18