GS8662Q08E GSI [GSI Technology], GS8662Q08E Datasheet - Page 16
GS8662Q08E
Manufacturer Part Number
GS8662Q08E
Description
72Mb SigmaQuad-II Burst of 2 SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8662Q08E.pdf
(35 pages)
- Current page: 16 of 35
- Download datasheet (2Mb)
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
READ
Notes:
1.
2.
3.
4.
Internal burst counter is fixed as 1-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.
“READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is
true for “WRITE” and “WRITE”.
Read and write state machine can be active simultaneously.
State machine control timing sequence is controlled by K.
Always
(Fixed)
Read Address
Read NOP
DDR Read
Load New
READ
READ
READ
16/35
State Diagram
Power-Up
WRITE
GS8662Q08/09/18/36E-300/250/200/167
WRITE
WRITE
Write Address
Write NOP
DDR Write
Load New
Always
(Fixed)
© 2005, GSI Technology
Preliminary
WRITE
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