GS8662S08E GSI [GSI Technology], GS8662S08E Datasheet - Page 26
GS8662S08E
Manufacturer Part Number
GS8662S08E
Description
72Mb Burst of 2 DDR SigmaSIO-II SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8662S08E.pdf
(37 pages)
- Current page: 26 of 37
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C Controlled Write-First Timing Diagram
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with the current IEEE Standard, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
drivers are powered by V
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Addr
BWx
R/W
CQ
CQ
LD
K
K
D
C
C
Q
NOP
IVKH
DD
.
A
Write A
AVKH
IVKH
KHAX
KHIX
KHKH
KHKH
KHKH
KHKH
A
B
A
26/37
Read B
KHKL
KHKL
IVKH
DVKH
KHIX
KHKL
KHKL
A+1
A+1
KLKH
KLKH
KHIX
KHDX
KLKH
KLKH
C
Write C
GS8662S08/09/18/36E-333/300/250/200/167
DD
KH#KH
or V
KH#KH
SS
. TDO should be left unconnected.
C
D
C
CHQX1
B
Write D
CQHQV
CHQX
C+1
C+1
B+1
CHQV
DD
CQHQX
D
E
D
. The JTAG output
Read E
CHQZ
© 2005, GSI Technology
D+1
D+1
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