GS88237BB GSI [GSI Technology], GS88237BB Datasheet

GS88237BB

Manufacturer Part Number

GS88237BB

Description

256K x 36 9Mb SCD/DCD Sync Burst SRAM

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS88237BB.pdf (29 pages)

Current page: 1 of 29
Download datasheet (761Kb)

119- & 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-bump and 165-bump BGA packages

• Pb-Free 119-bump and 165-bump BGA packages available

Functional Description

Applications

The GS88237BB/D is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx,

BW, GW) are synchronous and are controlled by a positive-

edge-triggered clock input (CK). Output enable (G) and power

down control (ZZ) are asynchronous inputs. Burst cycles can

be initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Rev: 1.04 3/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

9Mb SCD/DCD Sync Burst SRAM

Pipeline

3-1-1-1

3.3 V

2.5 V

Curr

tCycle

Parameter Synopsis

(x36)

1/29

256K x 36

-333

435

2.0

3.0

SCD and DCD Pipelined Reads

The GS88237BB/D is a SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM.

DCD SRAMs pipeline disable commands to the same degree

as read commands. SCD SRAMs pipeline deselect commands

one stage less than read commands. SCD RAMs begin turning

off their outputs immediately after the deselect command has

been captured in the input registers. DCD RAMs hold the

deselect command for one full cycle and then begin turning off

their outputs just after the second rising edge of clock. The user

may configure this SRAM for either mode of operation using

the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ

low) for multi-drop bus applications and normal drive strength

(ZQ floating or high) point-to-point applications. See the

Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88237BB/D operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output

power (V

internal circuits and are 3.3 V and 2.5 V compatible.

-300

395

2.2

3.3

-250 -200 Unit

330

DDQ

2.3

4.0

) pins are used to decouple output noise from the

270

2.7

5.0

GS88237BB/D-333/300/250/200

333 MHz–200 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS88237BB

GS88237BB Summary of contents

Page 1

... Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS88237BB/D operates 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V internal circuits and are 3.3 V and 2.5 V compatible. ...

Page 2

... DDQ NC A LBO DNU TMS TDI TCK TDO DDQ 2/29 GS88237BB/D-333/300/250/200 DDQ DDQ ...

Page 3

... TDI A1 TDO A A TMS A0 TCK A 3/29 GS88237BB/D-333/300/250/200 ADV ADSP DQB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ NC ...

Page 4

... DDQ Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-333/300/250/200 Description Address field LSBs and Address Counter Preset Inputs Address Inputs Data Input and Output pins Byte Write Enable for ...

Page 5

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237B Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q 5/29 GS88237BB/D-333/300/250/200 A Memory Array DQx1–DQx9 © 2002, GSI Technology ...

Page 6

... Note: The burst counter wraps to initial state on the 5th clock. 6/29 GS88237BB/D-333/300/250/200 Function Linear Burst Interleaved Burst Active Standby Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance) ...

Page 7

... may be used in any combination with BW to write single or multiple bytes. D 7/29 GS88237BB/D-333/300/250/200 B B Notes ...

Page 8

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 8/29 GS88237BB/D-333/300/250/200 First Read Burst Read BW, and GW) control inputs, and ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 9/29 GS88237BB/D-333/300/250/200 First Read Burst Read CR © 2002, GSI Technology ...

Page 10

... Symbol Min. V 3.0 DD3 V 2.3 DD2 V 3.0 DDQ3 V 2.3 DDQ2 +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 10/29 GS88237BB/D-333/300/250/200 Value –0.5 to 4.6 –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. ...

Page 11

... The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-333/300/250/200 Symbol Min. Typ. V 2.0 — ...

Page 12

... Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 12/29 GS88237BB/D-333/300/250/200 20% tKC Typ. Max. Unit 30pF © 2002, GSI Technology ...

Page 13

... DD Pipeline DDQ I Pipeline Pipeline and V operation. DD3 DD2 DDQ3 DDQ2 13/29 GS88237BB/D-333/300/250/200 Min – ≥ V – ≤ V – –1 uA OUT DD = 2.375 V 1.7 V DDQ = 3.135 V 2.4 V DDQ = 8 mA — -300 -250 ...

Page 14

... GS88237BB/D-333/300/250/200 -250 -200 Min Max Min Max — 4.0 — 5.0 — 2.2 — 2.3 — 2.7 1.0 1.0 — — — 1.0 1.0 — — — — 1.2 — 1.4 — 0.2 0.4 — ...

Page 15

... Pipeline Mode Timing (+1) Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKC tKC tKH tKH tKL tKL ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH Q(A) D(B) 15/29 GS88237BB/D-333/300/250/200 Deselect Deselected with E1 tKQX tLZ tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2002, GSI Technology ...

Page 16

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 16/29 GS88237BB/D-333/300/250/200 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2002, GSI Technology ...

Page 17

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-333/300/250/200 Description 17/29 © 2002, GSI Technology ...

Page 18

... JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 18/29 GS88237BB/D-333/300/250/200 · · TDO © 2002, GSI Technology ...

Page 19

... Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Not Used Configuration 19/29 GS88237BB/D-333/300/250/200 GSI Technology I/O JEDEC Vendor ID Code © 2002, GSI Technology 0 1 ...

Page 20

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 20/29 GS88237BB/D-333/300/250/200 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2002, GSI Technology ...

Page 21

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-333/300/250/200 21/29 © 2002, GSI Technology ...

Page 22

... Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Conditions V – DDQ V /2 DDQ Description 22/29 GS88237BB/D-333/300/250/200 JTAG Port AC Test Load * 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance Notes © ...

Page 23

... OLJC +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. DDn supply. DDQ JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS 23/29 GS88237BB/D-333/300/250/200 Min. Max. Unit Notes V +0.3 2.0 V DD3 0.8 V –0.3 0 +0.3 V DD2 DD2 ...

Page 24

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Min Max Unit 50 — ns — — ns — — — ns 24/29 GS88237BB/D-333/300/250/200 © 2002, GSI Technology ...

Page 25

... SEATING PLANE C Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-333/300/250/200 BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) ...

Page 26

... SEATING PLANE C Rev: 1.04 3/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88237BB/D-333/300/250/200 BOTTOM VIEW Ø0. Ø0. Ø0.40~0.50 (165x 1.0 10.0 13±0.07 B 0.20(4x) ...

Page 27

... GS88237BGD-333 256K x 36 GS88237BGD-300 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88237BB-200IB Commercial Temperature Range GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet ...

Page 28

... GS88237BGD-250I 256K x 36 GS88237BGD-200I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88237BB-200IB Commercial Temperature Range GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet ...

Page 29

... Removed 275 & 225 MHz speed bins • Updated mechanical drawings and added variation numbers Content to ordering information • Added Pb-Free information Content • Corrected block diagram (added E2 & E3 references) • Added /PE information to pin description table 29/29 GS88237BB/D-333/300/250/200 Page;Revisions;Reason © 2002, GSI Technology ...

Related keywords

GS88237BB datasheet
GS88237BB data sheet
GS88237BB pdf datasheet
GS88237BB component
GS88237BB part
GS88237BB distributor
GS88237BB RoHS
GS88237BB datasheet download