932S805CGLF IDT [Integrated Device Technology], 932S805CGLF Datasheet - Page 10

• Manufacturer Part Number: 932S805CGLF
• Description: K8 Clock Chip for Serverworks HT2100 Servers
• Manufacturer: IDT [Integrated Device Technology]

IDT
Bytes 11:14 Are Reserved
SMBus Table: CPU/SRC Frequency Control Register
SMBus Table: CPU/SRC Frequency Control Register
SMBus Table: CPU/SRC Spread Spectrum Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
®
Byte 15
Byte 16
Byte 17
K8 Clock Chip for Serverworks HT2100 Servers
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Div8
N Div9
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Name
Name
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Spread Spectrum Programming bit(7:0)
N Divider Programming Byte12 bit(7:0)
M Divider Programming
N Divider Prog bit 8
N Divider Prog bit 9
and Byte11 bit(7:6)
Control Function
Control Function
Control Function
bit (5:0)
10
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
[NDiv(9:0)+8] / [MDiv(5:0)+2]
[NDiv(9:0)+8] / [MDiv(5:0)+2]
in or Byte 0 Rom table. VCO
in or Byte 0 Rom table. VCO
These Spread Spectrum bits
of M and N Divier in Byte 15
of M and N Divier in Byte 15
pecentage of CPU and SRC
Default at power up = latch-
Default at power up = latch-
The decimal representation
The decimal representation
and 16 will configure the
and 16 will configure the
Frequency = 14.318 x
Frequency = 14.318 x
CPU VCO frequency.
CPU VCO frequency.
in Byte 17 and 18 will
program the spread
0
0
0
outputs.
1
1
1
1131D – 05/04/10
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X