MF1ICS2005 NXP [NXP Semiconductors], MF1ICS2005 Datasheet - Page 2

• Manufacturer Part Number: MF1ICS2005
• Description: Sawn bumped 120?m wafer addendum
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
141130
Product data sheet
1.Pads VSS and TESTIO are disconnected when wafer is sawn.
3.5 Au bump
3.6 Fail die identification
Remark: Substrate is connected to VSS.
Electronic wafer mapping covers the electrical test results and additionally the results of
mechanical/ visual inspection.
No inkdots are applied.
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Thickness:
Bump material:
Bump hardness:
Bump shear strength:
Bump height:
Bump height uniformity:
– within a die:
– within a wafer:
– wafer to wafer:
Bump flatness:
Bump size:
– LA, LB, VSS
– TESTIO
Bump size variation:
Under bump metallization:
1
1
Rev. 3.0 — 18 July 2007
500 nm / 600 nm
> 99.9% pure Au
35 – 80 HV 0.005
> 70 MPa
18 µm
± 2 µm
± 3 µm
± 4 µm
± 1.5 µm
104 x 104 µm
89 x 104 µm
± 5 µm
sputtered TiW
Sawn bumped 120µm wafer addendum
MF1 IC S20 05
© NXP B.V. 2007. All rights reserved.
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