DMA2275 MICRONAS [Micronas], DMA2275 Datasheet - Page 12

• Manufacturer Part Number: DMA2275
• Description: DMA 2275, DMA 2286 C/D/D2-MAC Descrambler
• Manufacturer: MICRONAS [Micronas]

Line
622
623
624
625
DMA 2275, DMA 2286
8. Interface Processor
The interface processor consists of:
– Fast Processor
– IM Bus Interface
– DRAM Interface
8.1. Fast Processor
The fast processor (FP) is a RISC–type 12 bit microcon-
troller built in CMOS technology. The maximum clock
frequency of 40 MHz and the internal architecture that
allows parallel ALU operation and data transfer to or
from internal RAM, make it applicable for very high
speed tasks, such as control and parameter calculation
in digital signal processors.
The FP is embedded in the DMA 2275 or DMA 2286 with
256 x 12 bit RAM and 2K x 20 bit ROM and runs with
20.25 MHz. The FP performs the following tasks:
– data transfer to and from DRAM interface
– data transfer to and from IM Bus interfaces
Fig. 8–1: Task manager
12
1
2
3
4
5
6
7
8
line_sync
line_sync
line_sync
line_sync
line_sync
line_sync
line_sync
line_sync
line_sync
line_sync
line_sync
line_
sync
prbs2
prbs2
prbs2
prbs2
prbs2
prbs2
prbs2
prbs2
prbs2
prbs2
prbs2
manager
manager
manager
manager
manager
manager
manager
manager
manager
manager
line_625_store
vcw_update
dcw1_update
dcw3_update
cw_conversion
psc_update
prbs_init
packet acquisition
imbus
pae_low_update
pae_high_update
mode_update
line_625_sync
pab_update
dcw2_update
dcw4_update
prbs2_init
disable_imbus
coeff_update
– support of packet acquisition
– support of line 625 acquisition
– initialization of PRBS generators
– control of video descrambler
– control of interpolation filter
Fig. 8–1 shows roughly when the different FP tasks are
executed within a frame period.
In normal operation the FP will not be directly accessed
from outside, that means that the CCU software will not
see another processor on the descrambling chip but
only a set of registers and buffers which are located ei-
ther in the acquisition DRAM or in the FP internal
memory. The CCU can access both memories via IM
Bus.
Changing any register in the DRAM memory by CCU
software will not effect the descrambler hardware im-
mediately. The FP will read or update the DRAM
memory only on frame boundaries, i.e. from line 622 to
line 7 inclusive. Changing registers in the FP memory by
CCU software will effect the descrambler hardware im-
mediately.
enable_imbus
packet_sync
packet_read
pae_comparator
buffer_manager
packet_link
packet_store
packet_error
disable_packet_sync
enable_packet_sync