DMA2275 MICRONAS [Micronas], DMA2275 Datasheet - Page 14

• Manufacturer Part Number: DMA2275
• Description: DMA 2275, DMA 2286 C/D/D2-MAC Descrambler
• Manufacturer: MICRONAS [Micronas]

DMA 2275, DMA 2286
Table 8–1: Data transfer between CCU and DMA 2275/2286
14
Addr.
No.
203
194
195
196
197
198
204
205
206
208
209
210
10
5
6
7
8
9
Bit must be set to zero for write registers (W) and are
don’t care for read registers (R)
Direct.
W
W
W
R/W
R
W
W
W
W
W
W
W
W
W
R
R
R
R
Bit
No.
TT15
TT15
MSB
15
DRS
Select
Data
Rate
S
S
S
S
S
0
0
0
0
1
0
0
Select
Chip
CS
0
Coding Law CH4
Channel Mode
Channel Mode
Channel Mode
Channel Mode
TT14
TT14
P0S
AUM
Mode
14
HQ
HQ
HQ
HQ
Auto
HQ
0
0
0
0
0
0
0
C1M
C2M
C3M
C4M
C4L
this is an 8 bit register
this is an 8 bit register
TT13
TT13
C4S
Packet 0 Syndrom High Byte
Defin.
13
Chip
CD
H
H
H
H
0
H
0
0
0
0
0
1
0
Packet 0 Data High Byte
Status
TT12
TT12
C3S
12
0
0
0
L
L
L
L
0
0
L
0
0
0
PSH
PDH
Update
Update
Update
Update
TT11
TT11
C2S
C1U
C2U
C3U
C4U
Mode
Mode
Mode
Mode
11
S
0
0
0
0
0
0
0
0
0
Coding Law CH3
Channel
Channel
Channel
Channel
Disable
TT10
Enable
Enable
Enable
Enable
TT10
C1S
DSB
S Bus
C1E
C2E
C3E
C4E
10
HQ
0
0
0
0
0
1
0
0
0
C3L
P0C
TT9
Clear
TT9
P0
H
9
0
0
0
0
0
P0R
Reset
TT8
TT8
P0
8
0
L
0
0
0
0
TT7
TT7
S
7
0
0
0
0
Data Group Type
Coding Law CH2
TT6
TT6
HQ
6
0
0
0
DGT
C2L
0
Extension Data
Packet 0 Syndrom Low Byte
TT5
TT5
5
H
0
0
0
Packet 0 Data Low Byte
Channel Packet Address
Channel Packet Address
Channel Packet Address
Channel Packet Address
EXD
Extension Address
0
Subframe Select
Write Address
Read Address
Bit Error Rate
TT4
TT4
4
L
0
0
0
PDL
WRA
BER
PSL
RDA
Data
EXA
DAT
C1A
C2A
C3A
C4A
SFS
106
82
0
0
0
0
0
0
0
TT3
TT3
S
3
0
0
0
Coding Law CH1
S Bus Enable
BUS
TT2
TT2
Busy
HQ
2
0
0
0
0
SBE
C1L
12
Request
RRQ
Read
TT1
TT1
1
H
0
0
0
0
Request
WRQ
Write
LSB
TT0
TT0
0
L
0
0
0
0