LV4904V SANYO [Sanyo Semicon Device], LV4904V Datasheet
LV4904V
Related parts for LV4904V
LV4904V Summary of contents
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... LV4904V Overview The LV4904V is a 2-channel class-D amplifier IC that supports digital input. With this single chip and with a minimal number of external components possible to effectively implement class-D amplifiers. The LV4904V incorporates a soft mute function and a gain controller without pop noise, and can be used as a master volume control of the set. Its ...
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... The maximum power transistor ON resistance(R DS ON) is 360mΩ(design guarantee value). Note : The value of these characteristics were measured in SANYO test environment. The actual value in an end system will vary depending on the printed circuit board pattern, the components used, and other factors. LV4904V Conditions Externally applied power supply ...
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... BOTTOM VIEW Exposed Die-Pad 23 22 0.2 SANYO : SSOP44J(275mil) Pd max -- Ta Specified board : 85.0 × 59.0 × 1.5mm 3 glass epoxy(2-layer) 1.32 1. Ambient temperature LV4904V 120 Top view ...
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... DFORM0 Control Signal DFORM1 DFORM2 MCKFS SRATE PTAB2 PVD2 OUT_CH2_P BOOT_CH2_P BOOT_CH2_N OUT_CH2_N PGND2 PGND2 3.3V LV4904V SCL SDA GAIN0 GAIN1 GAIN2 GAIN3 GAIN4 GAIN5 MUTEB MODE TEST PTAB1 PVD1 OUT_CH1_P BOOT_CH1_P BOOT_CH1_N OUT_CH1_N ...
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... GAIN0 42 GAIN1 41 CONTROLLER GAIN2 40 GAIN3 39 GAIN4 38 GAIN5 37 MUTEB 36 MODE 35 TEST 34 SDA I/F SCL 44 LV4904V OUTPUT STAGE PWM CH1+ RECEIVER CONTROL DELAY PWM OUTPUT RECEIVER STAGE CH1- THERMAL SEQUENCE OVER CURRENT OUTPUT STAGE PWM CH2- RECEIVER CONTROL DELAY PWM OUTPUT RECEIVER ...
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... Channel 1 power ground 25 OUT_CH1_N O Output pin, channel 1 (Lch BOOT_CH1_N I/O Bootstrap I/O pin, channel 1 (Lch De-coupling capacitor connection pin for internal power supply 28 I/O Bootstrap I/O pin, channel 1 (Lch) + BOOT_CH1_P LV4904V Description Equivalent Circuit PVD 16 GND PVD 20 GND PVD 25 GND Continued on next page. No.A1963-6/25 ...
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... GAIN4 DI Gain setting input 4 39 GAIN3 DI Gain setting input 3 40 GAIN2 DI Gain setting input 2 41 GAIN1 DI Gain setting input 1 42 GAIN0 DI Gain setting input SDA DIO [I C I/F] data 2 44 SCL I/F] bit clock LV4904V Description Equivalent Circuit PVD 29 GND 44 No.A1963-7/25 ...
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... Pin setting mode In this mode, the LV4904V is controlled only by pin settings. This has the advantage of not requiring the I for control purposes, but the parameters that can be set are limited. Table 1.1 below lists the differences between the items that can be set through the I Table 1 ...
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... Description of Pin Functions 2.1 Hardware reset pin (RSTB) RSTB is a low active hardware reset pin. The LV4904V is initialized by setting this pin to low. When the pin is set to low, the internal registers are cleared, and 2 the I C bus registers are also reset to the initial values. ...
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... SRATE is low. Since the initial setting of the I is the setting that is established when SRATE is low in the initial state after reset release. Table 2.8 shows the SRATE function settings. SRATE Combined LV4904V Table 2.6 Input data format settings DFORM0 2 Combined I C Bus and Pin setting Mode 2 ...
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... MUTEB Combined 2.11 Test mode setting pins (TEST, MODE) TEST and MODE are the test pins. TEST and MODE must be low while using the LV4904V. Table 2.11 shows the TEST, MODE function settings. Table 2.11 TEST, MODE pin settings TEST, MODE L Setting when using the LV4904V ...
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... MUTEBR_Reg 3.2 Stop sequence PVD V DD ENABLE RSTB MUTEB MUTEBL_Reg MUTEBR_Reg OUT_1P/1N OUT2P/2N OUT1P/1N OUT2P/2N (After demodulation) LV4904V PVD and V DD may >8.0V be started up in any sequence. >3.0V >2ms Figure 3.1 Start sequence >1ms >200ms Figure 3.2 Stop sequence >50ms PVD and V DD may be stopped in any sequence ...
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... Protection Circuits The LV4904V is provided with under voltage protection circuit, overcurrent protection circuit and thermal protection circuit. 4.1 Under voltage protection circuit In order to prevent unstable operation at low voltages, the under voltage protection circuit monitors the PVD pin voltage, and once the attack voltage (PVD=7V typ.) has been exceeded, it turns on the amplifier. Furthermore, the recovery voltage (6V typ ...
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... ICs will not be damaged. Figures 4.2.1 and 4.2.2 show the operating models of the overcurrent protection circuit. Output Current Control Operation Internal Control Signal Figure 4.2.1 Graphical representation of overcurrent protection circuit operation IDETECT Output Current Internal Control Signal Figure 4.2.2 Graphical representation of overcurrent protection circuit operation (enlarged) LV4904V Self-recovery & Normal Operation HOLD TIME No.A1963-14/25 ...
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... However, the thermal protection circuit is a function that temporarily prevents abnormal internal heat generation and does not guarantee that the ICs will not be damaged. Similarly, the operating temperature of the thermal protection circuit is not a guaranteed value. Figure 4 graphical representation of the thermal protection circuit. LV4904V Output Current Control Operation Internal Control Signal Figure 4 ...
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... Data transfer is started after the start condition has been transmitted. The data is transferred in 8-bit units from the master to the LV4904V at the slave, and the LV4904V responds every time 8 bits are received by setting the SDA pin to low. This is referred to as acknowledge (ACK). The master sets the bus free and waits for ACK. ...
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... Data read By sending the data read command, the data held in the registers of the LV4904V can be read. To read the data, first the address is sent using a dummy write cycle, and then operation is restarted. Next, after the device ID and read flag has been sent in the read cycle, the LV4904V outputs the data of the address sent in the dummy write cycle to the SDA line. ...
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... Lch Figure 8.1.4 [DFORM_I C = 011/100/101/110] BCK=64 fs, 24/20/18/16 bits, right justified, MSB first 32fs Lch LV4904V MCKFS_I C [1: 0] SRATE_I valid only when the DFORM0, DFORM1, and DFORM2 pins are Data Format Left justified, MSB first ...
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... LV4904V 2 C are set in accordance with the master clock and input sample 2 C are valid only when the MCKFS pin is set to low in the combined 2 C are valid only when the SRATE pin is low in the combined setting described here is ignored. ...
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... Table 8.3.2 MDIDX function settings (initial value in bold). MDIDX 0 87.5% 1 100% The noise shaper order can be switched by setting NSORD. Table 8.3.3 shows the NSORD function settings. Table 8.3.3 NSORD function settings (initial value in bold) NSORD 0 Seventh order 1 Fifth order LV4904V Setting Setting Reserved NSORD Setting Setting Setting D2 D1 ...
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... RSTB=High ENABLE=Low Power cell Power Supply, PVD - V I CCO -- PVD RSTB=High ENABLE=High MUTEB=Low Power cell Power Supply, PVD - V LV4904V 0 =3.3V RSTB=Low 0.8 0.6 0.4 0.2 0 3.6 3.8 4.0 -40 0.5 PVD=15V RSTB=Low 0.4 0.3 0.2 0 -40 6 VD=15V ...
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... Power cell Power Supply, PVD - V CH sep. -- PVD =1kHz VO=0dBm D IN AUDIO -20 -40 -60 - Power cell Power Supply, PVD - V LV4904V VD=15V RSTB=High ENABLE=High MUTEB=Low 0 3.8 4.0 -40 - VD=15V RSTB=High ...
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... PVD=15V PO=1W 2CH-Drive Vol=+12dB 1 AES17 0.1 0.01 10 100 1000 10000 Frequency - Hz THD+N -- Power 10 1 0.1 PVD=15V 2CH-Drive Vol=+12dB AES17 0.01 0.0001 0.001 0.01 0.1 Power - W LV4904V PVD=15V =1kHz 5 THD+N=10% 2CH-Drive AES17 -40 -20 10 PVD=15V PO=1W 2CH-Drive Vol=+12dB 1 AES17 0.1 0. ...
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... Power - W Response -- Frequency 10 PVD=15V PO=1W 6 2CH-Drive Vol=+12dB 4 AES17 -10 10 100 1000 10000 Frequency - Hz LV4904V 100 PVD=15V =1kHz 10 2CH-Drive Vol=+12dB 1 AES17 0.1 PVD=15V 0. =1kHz 0.001 2CH-Drive AES17 0.0001 PVD=15V =1kHz ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of September, 2011. Specifications and information herein are subject to change without notice. LV4904V PS No.A1963-25/25 ...