LV4904V SANYO [Sanyo Semicon Device], LV4904V Datasheet - Page 10

• Manufacturer Part Number: LV4904V
• Description: Digital Input Class-D Power Amplifier
• Manufacturer: SANYO [Sanyo Semicon Device]

2.6 Input data format setting pins (DFORM0, DFORM1, DFORM2)
2.7 Master clock setting pin (MCKFS)
2.8 Sample rate setting pin (SRATE)
The DFORM0, DFORM1 and DFORM2 pins are set to high or low to match the data format that is input.
In the combined I
register are valid when DFORM0, DFORM1, and DFORM2 are low. Since the initial setting of the I
I
release.
Table 2.6 shows the format settings established according to the DFORM0, DFORM1, and DFORM2 pins.
The MCKFS pin is set to high or low to match the rate of the master clock that is to be input from the MCK pin.
In the combined I
register are valid when MCKFS is low. Since the initial setting of the I
established when MCKFS is low in the initial state after reset release.
If the rate of the clock that is input from the MCK pin does not match the MCKFS pin or the setting established
according to the I
Table 2.7 shows the MCKFS function settings.
The SRATE pin is set to high or low to match the sample rate of the input data.
In the combined I
register are valid when SRATE is low. Since the initial setting of the I
is the setting that is established when SRATE is low in the initial state after reset release.
Table 2.8 shows the SRATE function settings.
2
S is the setting that is established when DFORM0, DFORM1, and DFORM2 are low in the initial state after reset
DFORM2
H
H
H
L
L
L
L
MCKFS
SRATE
H
H
L
L
2
2
2
2
C register, an abnormal sound is generated or the output is set to off.
C bus and pin setting mode, the master clock settings (Table 8.1.2) established according to the I
C bus and pin setting mode, the data format settings (Table 5.1.1) established according to the I
C bus and pin setting mode, the sample rate settings (Table 8.1.2) established according to the I
DFORM1
H
H
H
L
L
L
L
Combined I
Combined I
DFORM0
Table 2.7 MCKFS pin function settings
Table 2.8 SRATE pin function settings
I
I
2
2
2
2
C Bus and Pin setting mode
C register setting
C Bus and Pin setting mode
C register setting
H
H
H
L
L
L
L
Table 2.6 Input data format settings
LV4904V
Combined I
88.2 kHz/96 kHz
Setting
Setting
512 fs
I
2
2
C Bus and Pin setting Mode
C register setting
2
24-bit, right justified, MSB first
20-bit, right justified, MSB first
18-bit, right justified, MSB first
16-bit, right justified, MSB first
C register is 44.1 kHz/48 kHz, 44.1 kHz/48 kHz
2
C register is 256fs, 256fs is the setting that is
Right justified, LSB first
Left justified, MSB first
Pin Setting Mode
44.1 kHz/48 kHz
Pin Setting Mode
256 fs
Setting
Pin Setting Mode
I
2
S
2
C register is I
No.A1963-10/25
2
2
2
2
S,
C
C
C