LV4904V SANYO [Sanyo Semicon Device], LV4904V Datasheet - Page 9

• Manufacturer Part Number: LV4904V
• Description: Digital Input Class-D Power Amplifier
• Manufacturer: SANYO [Sanyo Semicon Device]

2. Description of Pin Functions
2.1 Hardware reset pin (RSTB)
2.2 System enable pin (ENABLE)
2.3 Master clock input pin (MCK)
2.4 3-wire serial data input pins (BCK, LRCK, SDIN)
2.5 I
RSTB is a low active hardware reset pin.
The LV4904V is initialized by setting this pin to low. When the pin is set to low, the internal registers are cleared, and
the I
Table 2.1 shows the RSTB function settings.
ENABLE is the system enable pin of the LV4904V.
When this pin is set to low, the output is muted regardless of any other settings (mute, gain), and the PWM output is
stop(set to high-impedance). ENABLE must be set to high in order to activate the LV4904V.
If the ENABLE function does not need to be set to ON or OFF, the ENABLE pin can be fixed at high.
Table 2.2 shows the ENABLE function settings.
The master clock is input from the MCK pin.
For details on this pin, refer to “8.1 Input data settings.”
BCK, LRCK and SDIN are pins used for 3-wire serial data input.
For details on these pins, refer to “8.1 Input data settings.”
SCL and SDA are the pins used for I
The I
SCL is the I
pulling the SCL line to low. SDA is the I
be pulled up.
For details on the I
2
C bus pins (SCL, SDA)
2
C bus registers are also reset to the initial values.
2
C bus interface of the LV4904V does not function as the master but operates only as a slave.
2
C bus clock pin and operates only as an input pin. This means that the LV4904V never requests wait by
Table 2.1 RSTB pin functions
Table 2.2 ENABLE pin function settings
2
C bus interface, refer to “5 I
ENABLE
RSTB
H
H
L
L
Hardware reset (registers cleared)
System disabled
For normal operation
System enabled
2
C bus communication.
2
C bus data pin, and since it is an N-channel open drain pin, the data line must
2
C Bus Specifications.”
Setting
LV4904V
Setting
No.A1963-9/25