LV4904V SANYO [Sanyo Semicon Device], LV4904V Datasheet - Page 19

• Manufacturer Part Number: LV4904V
• Description: Digital Input Class-D Power Amplifier
• Manufacturer: SANYO [Sanyo Semicon Device]

Master clock rate MCKFS_I
rate. The settings established according to MCKFS_I
I
according to the pins described in section 2.7 are valid, therefore MCKFS_I
settings established according to SRATE_I
setting mode. When SRATE is high or when the pin setting mode is established, the settings established according to the
pins described in section 2.8 are valid, therefore SRATE_I
If these settings are illegal and they do not match the input signals, an abnormal sound is generated or the output is set to
off. Noise is generated when switching the settings, so mute the output before changing any settings.
Table 8.1.2 shows the settings of the master clock that is set by SRATE and MCKFS.
Table 8.1.2 Master clock settings (initial values in bold)
8.2 Gain and mute settings
2
C bus and pin setting mode. When MCKFS is high or when the pin setting mode is established, the settings established
The left-channel volume and right-channel volume are each set with 6 bits and in 64 steps using the GAINL and
GAINR registers, respectively. The volume setting ranges from +12 dB to -81 dB in 1.5 dB increments.
The settings established according to GAINL and GAINR are valid only when all the GAIN0 to GAIN5 pins are low in
the combined I
settings established according to the pins described in section 2.9 are valid, therefore GAINL and GAINR setting
described here is ignored.
Table 8.2.1 shows the volume settings established according to GAINL and GAINR.
Table 8.2.1 Gain settings (initial value in bold)
Register
GAINR
GAINL
No.
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
2
[1]
C bus and pin setting mode. With any other pin settings or when the pin setting mode is established, the
0
0
1
1
SRATE_I
110101
110100
110010
110001
110000
101101
101100
101011
101010
GAINR
111101
111100
111011
111010
111001
111000
110111
110110
110011
101111
101110
GAINL
111111
111110
Address
21h
20h
2
C
[0]
0
1
0
1
2
C and sample rate SRATE_I
Gain (dB)
PSTPR
PSTPL
+12.0
+10.5
-10.5
-12.0
-13.5
-15.0
-16.5
-18.0
-19.5
+9.0
+7.5
+6.0
+4.5
+3.0
+1.5
D7
-1.5
-3.0
-4.5
-6.0
-7.5
-9.0
0.0
Sampling Rate
176.4/192 kHz
44.1/48 kHz
88.2/96 kHz
32 kHz
2
C are valid only when the SRATE pin is low in the combined I
MUTEBR
MUTEBL
D6
No.
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
2
LV4904V
C are valid only when the MCKFS pin is set to low in the combined
256 fs
256 fs
128 fs
64 fs
2
[00]
C are set in accordance with the master clock and input sample
2
C setting described here is ignored.
D5
101001
101000
100110
100101
100100
100011
100010
100001
100000
011010
011001
011000
010110
010101
010100
GAINR
100111
011110
011101
011100
011011
010111
GAINL
011111
MCKFS_I
384 fs
384 fs
192 fs
96 fs
[01]
D4
2
C Setting and MCK Rate
Gain (dB)
-21.0
-22.5
-24.0
-25.5
-27.0
-28.5
-30.0
-31.5
-33.0
-34.5
-36.0
-37.5
-39.0
-40.5
-42.0
-43.5
-45.0
-46.5
-48.0
-49.5
-51.0
-52.5
2
C setting described here is ignored. The
512 fs
512 fs
256 fs
128 fs
D3
[10]
GAINR [5:0]
GAINL [5:0]
No.
19
18
17
16
15
14
13
12
10
11
8
4
3
2
1
9
7
6
5
0
D2
768 fs
768 fs
384 fs
192 fs
[11]
010011
010010
010001
010000
001101
001100
001011
001010
001001
001000
000110
000101
000100
000011
000010
000001
000000
GAINR
001111
001110
000111
GAINL
D1
2
C bus and pin
No.A1963-19/25
Gain (dB)
MUTE
-54.0
-55.5
-57.0
-58.5
-60.0
-61.5
-63.0
-64.5
-66.0
-67.5
-69.0
-70.5
-72.0
-73.5
-75.0
-76.5
-78.0
-79.5
-81.0
D0