S5935TFC AMCC [Applied Micro Circuits Corporation], S5935TFC Datasheet - Page 149

• Manufacturer Part Number: S5935TFC
• Description: PCI Product
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

S5935 – PCI Product
MWARAllBus master write address
MRARAllBus master read address
It is recommended that bus mastering be enabled as
the last step. Some applications may choose to leave
bus mastering enabled (AMREN and AMWEN
asserted) and start transfers by writing a non-zero
value to the transfer count registers (if they are
enabled).
If interrupts are enabled, an Add-On CPU interrupt
service routine is also required. The service routine
determines the source of the interrupt and resets the
AMCC Confidential and Proprietary
5. Define PCI to Add-On and Add-On to PCI FIFO
6. Define
7. Define transfer byte counts. These registers are
MWTC
MRTC
8. Enable Bus Mastering. Once steps 1-7 are com-
MCSR
MCSR
priority. These bits determine which FIFO has pri-
ority if both meet the defined condition to request
the PCI bus. If these bits are the same, priority
alternates, with read accesses occurring first.
This must be programmed through the PCI
interface.
These registers are written with the first address
that is to be accessed by the S5935. These
address registers are updated after each access
to indicate the next address to be accessed.
Transfers must start on DWORD boundaries.
written with the number of bytes to be transferred.
The transfer count does not have to be a multiple
of four bytes. These registers are updated after
each transfer to reflect the number of bytes
remaining to be transferred. If transfer counts are
disabled, these registers do not need to be
programmed.
pleted, the FIFO may operate as a PCI bus
master. Read and write bus master operation
may be independently enabled or disabled. The
AMREN and AMWEN inputs control bus master
enabling for Add-On initiated bus mastering. The
MCSR bus master enable bits are ignored for
Add-On initiated bus mastering.
Bit 12
All
All
Bit 8
transfer
Read vs. write priority
Write vs. read priority
Write transfer byte count
Read transfer byte count
source/destination
address.
interrupt. As mailbox registers may also be configured
to generate interrupts, the exact source of the interrupt
is indicated in the Add-On Interrupt Control Register
(AINT). Typically, the interrupt service routine is used
to setup the next transfer by writing new addresses
and transfer counts (if enabled), but some applications
may also require other actions. If read transfer or write
transfer complete interrupts are enabled, the master/
target abort interrupt is automatically enabled. These
indicate a transfer error has occurred. Writing a one to
these bits clears the corresponding interrupt.
PASS-THRU OVERVIEW
The S5935 provides a simple registered access port to
the PCI bus. Using a handshaking protocol with Add-
On card logic, the PCI bus directly accesses resources
on the Add-On. The Pass-Thru data transfer method is
very useful for direct Add-On memory access, or
accessing registers within peripherals on an Add-On
board. Pass-Thru operation requires an external nv
memory boot device to define and configure the
S5935 Pass-Thru regions.
The S5935 provides four user-configurable Pass-Thru
regions. Each region corresponds to a PCI Configura-
tion Base Address Register (BADR1-4). A region
represents a block of address space (the block size is
user-defined). Each block can be mapped into mem-
ory or I/O space. Memory mapped regions can request
to be located below 1 MByte (Real Mode address
space for a PC). Each region also has a configurable
bus width for the Add-On bus interface. An 8-, 16-, or
32-bit Add-On interface may be selected, for use with
a variety of Add-On memory or peripheral devices.
Pass-Thru features can be used only when the S5935
is a PCI target. As a target, the S5935 Pass-Thru
mode supports single data transfers as well as burst
transfers. When accessed with burst transfers, the
S5935 supports data transfers at the full PCI band-
width. The data transfer rate is only limited by the PCI
initiator performing the access and the speed of the
Add-On logic.
FUNCTIONAL DESCRIPTION
To provide the PCI bus Add-On with direct access to
Add-On resources, the S5935 has an internal Pass-
AINT
AINT
AINT
Bit 21
Bit 19
Bit 18
Master/target abort caused interrupt
Read transfer complete caused interrupt
Write transfer complete caused interrupt
Revision 1.02 – June 27, 2006
Data Book
DS1527
149