S5935TFC AMCC [Applied Micro Circuits Corporation], S5935TFC Datasheet - Page 68

• Manufacturer Part Number: S5935TFC
• Description: PCI Product
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

S5935 – PCI Product
INTERRUPT CONTROL/STATUS REGIS-
TER (INTCSR)
Figure 29. Interrupt Control/Status Register
68
Register Name
PCI Address
Offset
Power-up value
Attribute
Size
DS1527
Interrupt Asserted (RO)
Target Abort (R/WC)
Master Abort (R/WC)
Read Transfer
Complete (R/WC)
Write Transfer
Complete (R/WC)
Incoming Mailbox
Interrupt (R/WC)
Outgoing Mailbox
Interrupt (R/WC)
31
FIFO and Endian Control
Interrupt Control and Status
38h
00000000h
Read/Write (R/W), Read/
Write_One_Clear (R/WC)
32 bits
24
23
0
Actual Interrupt
21
16
15 14
0
12
This register provides the method for choosing which
conditions are to produce an interrupt on the PCI bus
interface, a method for viewing the cause of the inter-
rupt, and a method for acknowledging (removing) the
interrupt’s assertion.
Interrupt sources:
Interrupt Selection
8
•
•
•
•
•
•
0 0 0
Write Transfer Terminal Count = zero
Read Transfer Terminal Count = zero
One of the Outgoing mailboxes (1,2,3 or 4)
becomes empty
One of the Incoming mailboxes (1,2,3 or 4)
becomes full.
Target Abort
Master Abort
4
Interrupt Source (R/W)
Enable & Selection
D4-D0 Outgoing Mailbox
D4=Enable Interrrupt
D3-D2=Mailbox #
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
D1-D0=Byte #
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
D12-D8 Incoming Mailbox (R/W)
D12=Enable Interrupt
D11-D10=Mailbox
0 0=Mailbox 1
0 1=Mailbox 2
1 0=Mailbox 3
1 1=Mailbox 4
D9-D8=Byte #
0 0=Byte 0
0 1=Byte 1
1 0=Byte 2
1 1=Byte 3
Interrupt on Write
Transfer Complete
Interrupt on Read
Transfer Complete
0
Revision 1.02 – June 27, 2006
(Goes empty)
(Becomes full)
AMCC Confidential and Proprietary
Bit
Value
Data Book