AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 100
AX500-1BG896
Manufacturer Part Number
AX500-1BG896
Description
Axcelerator Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.AX500-1BG896.pdf
(226 pages)
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Figure 2-68 • FIFO Read Timing
Table 2-97 • One FIFO Block
2 -8 6
Parameter
FIFO Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WSU
WHD
WCKH
WCKL
WCKP
RSU
RHD
RCKH
RCKL
RCKP
CLRHF
CLR2FF
CLR2AF
CK2FF
CK2AF
RCK2RD1
RCK2RD2
Axcelerator Family FPGAs
RCLK
FREN
RD <35:0>
CLR
EMPTY, AEMPTY, AFULL, FULL
Worst-Case Commercial Conditions V
Write Setup
Write Hold
WCLK High
WCLK Low
Minimum WCLK Period
Read Setup
Read Hold
RCLK High
RCLK Low
Minimum RCLK period
Clear High
Clear-to-flag (EMPTY/FULL)
Clear-to-flag (AEMPTY/AFULL)
Clock-to-flag (EMPTY/FULL)
Clock-to-flag (AEMPTY/AFULL)
RCLK-To-OUT (Pipelined)
RCLK-To-OUT (Non-Pipelined)
Description
t
CLRHF
t
RCKP
CCA
= 1.425V, V
t
RSU
v2.7
t
CLR2xF
t
t
RHD
RCK2RD1
t
Min.
2.42
RCKH
2.3
'–2' Speed
CCI
= 3.0V, T
Max.
4.62
1.08
0.22
0.98
1.15
0.81
0.00
1.00
1.21
1.08
2.02
2.24
5.31
1.39
2.62
t
J
RCKL
= 70°C
Min.
2.76
2.6
'–1' Speed
t
t
RCK2RD2
CK2xF
Max.
1.23
0.25
1.11
1.30
0.92
0.00
1.14
1.38
1.23
5.26
6.05
2.55
1.59
2.98
2.3
Min.
3.06
3.24
'Std' Speed
Max.
1.45
0.30
1.31
1.53
1.08
0.00
1.34
1.62
1.45
6.19
7.11
1.86
2.7
3.5
3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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