AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 81

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Special PLL Macros
Table 2-83
resources.
Table 2-83 • PLL Special Macros
Table 2-84 • Electrical Specifications
Macro Name
PLLINT
PLLRCLK
PLLHCLK
PLLOUT
Parameter
Frequency Ranges
Reference Frequency (min.)
Reference Frequency (max.)
OSC Frequency (min.)
OSC Frequency (max.)
Jitter
Long-Term Jitter (max.)
Long-Term Jitter (max.)
Short-Term Jitter (max.)
Acquisition Time (lock) from Cold Start
Acquisition Time (max.)*
Acquisition Time (max.)*
Power Consumption
Analog Supply Current (low freq.)
Analog Supply Current (high freq.)
Digital Supply Current (low freq.)
Digital Supply Current (high freq.)
Duty Cycle
Minimum Output Duty Cycle
Maximum Output Duty Cycle
Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency.
shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing
Connects RefCLK to a regular routed net or a pad.
Connects CLK1 or CLK2 to the CLK network.
Connects CLK1 or CLK2 to the HCLK network.
Connects CLK1 or CLK2 to a regular routed net.
0.5
1μ
400 cycles
50ps+1%
200 MHz
14 MHz
20 MHz
200
Value
200μA
μA/MHz
1 GHz
100ps
1.5 μs
A/MHz
45%
55%
1%
μA
v2.7
Lowest input frequency
Highest input frequency
Lowest output frequency
Highest output frequency
Percentage of period, low reference clock frequencies
High reference clock frequencies
Percentage of output frequency
Period of low reference clock frequencies
High reference clock frequencies
Current at minimum oscillator frequency
Frequency-dependent current
Current at maximum oscillator frequency, unloaded
Frequency-dependent current
Usage
Notes
Axcelerator Family FPGAs
2-67