AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 29

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Table 2-14 • Bank-Wide Delay Values
Using the Differential I/O Standards
Differential I/O macros should be instantiated in the
netlist. The settings for these I/O standards cannot be
changed inside Designer. Please note that there are no
tristated or bidirectional I/O buffers for differential
standards.
Bits Setting
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note: Delay values are approximate and will vary with process,
• The slew-rate value for the LVTTL output buffer
• The drive strength value for LVTTL output buffers
5. These values are minimum drive strengths.
activated by default to ensure a zero hold-time.
The default setting for this property can be set in
Designer. When the input buffer does not drive a
register, the delay element is deactivated to
provide higher performance. Again, this can be
overridden by changing the default setting for this
property in Designer.
can be programmed and can be set to either slow
or fast.
can be programmed as well. There are four
different drive strength values – 8mA, 12mA,
16mA, or 24mA – that can be specified in
Designer.
temperature, and voltage.
Delay (ns)
5
0.54
0.65
0.71
0.83
1.01
1.08
1.19
1.27
1.39
1.45
1.56
1.64
1.75
1.81
1.93
0.9
Bits Setting Delay (ns)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.01
2.13
2.19
2.38
2.49
2.55
2.67
2.75
2.87
2.93
3.04
3.12
3.23
3.29
3.41
2.3
v2.7
Using the Voltage-Referenced I/O Standards
Using these I/O standards is similar to that of single-
ended I/O standards. Their settings can be changed in
Designer.
Using DDR (Double Data Rate)
In Double Data Rate mode, new data is present on every
transition of the clock signal. Clock and data lines have
identical bandwidth and signal integrity requirements,
making it very efficient for implementing very high-
speed systems.
To implement a DDR, users need to:
1. Instantiate an input buffer (with the required I/O
2. Instantiate the DDR_REG macro
3. Connect the output from the Input buffer to the
Figure 2-6 • DDR Register
Macros for Specific I/O Standards
There are different macro types for any I/O standard or
feature that determine the required V
voltages for an I/O. The generic buffer macros require
the LVTTL standard with slow slew rate and 24mA-drive
strength. LVTTL can support high slew rate but this
should only be used for critical signals.
Most of the macro symbols represent variations of the six
generic symbol types:
Other macros include the following:
standard)
input of the DDR macro
• CLKBUF: Clock Buffer
• HCLKBUF: Hardwired Clock Buffer
• INBUF: Input Buffer
• OUTBUF: Output Buffer
• TRIBUF: Tristate Buffer
• BIBUF: Bidirectional Buffer
• Differential I/O standard macros: The LVDS and
LVPECL macros either have a pair of differential
D
D
CLK
CLR
PSET
QR
QF
Axcelerator Family FPGAs
(Figure
2-6)
CCI
and V
2-15
REF