AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 23

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

I/O Specifications
Pin Descriptions
Supply Pins
GND
Low supply voltage.
V
Supply voltage for array (1.5V). See
Conditions" on page 2-1
V
Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See
"Operating
information.
V
Supply voltage for the I/O differential amplifier and JTAG
and probe interfaces. See
page 2-1
3.3V.
V
PLL analog power supply (1.5V) for internal PLL. There
are eight in each device. V
associated with global resource HCLKA, V
the PLL associated with global resource HCLKB, etc. The
PLL analog power supply pins should be connected to
1.5V whether PLL is used or not.
V
Compensation reference signals for internal PLL. There
are eight in each device. V
associated
supports the PLL associated with global resource CLKE,
etc. (see
connection to the supply). The V
left floating if PLL is not used.
V
In the low power mode, V
external charge pump (if the user desires to bypass the
internal charge pump to further reduce power). The
device starts using the external charge pump when the
voltage level on V
operation, when using the internal charge pump, V
should be tied to GND.
CCA
CCIBx
CCDA
CCPLA/B/C/D/E/F/G/H
COMPLA/B/C/D/E/F/G/H
PUMP
1. When V
for more information. V
Figure 2-2 on page 2-9
with
PUMP
Conditions"
= V
Ground
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage (External Pump)
Supply Voltage
global
PUMP
IH
, it shuts off the internal charge pump. See
for more information.
reaches V
PUMP
"Operating Conditions" on
resource
on
COMPLA
CCPLA
will be used to access an
CCDA
COMPLX
page 2-1
IH
for correct external
1
. In normal device
supports the PLL
supports the PLL
HCLKA,
should be tied to
pins should be
CCPLB
"Operating
for
supports
V
COMPLE
more
PUMP
v2.7
"Low Power Mode" on page
Figure 2-2 • V
User-Defined Supply Pins
V
Reference voltage for I/O banks. V
by the user from regular I/O pins; V
fixed locations. There can be one or more V
I/O bank.
Global Pins
HCLKA/B/C/D
These pins are the clock inputs for sequential modules or
north PLLs. Input levels are compatible with all
supported I/O standards. There is a P/N pin pair for
support of differential I/O standards. Single-ended clock
I/Os can only be assigned to the P side of a paired I/O.
This input is directly wired to each R-cell and offers clock
speeds independent of the number of R-cells being
driven. When the HCLK pins are unused, it is
recommended that they are tied to ground.
CLKE/F/G/H
These pins are clock inputs for clock distribution
networks or south PLLs. Input levels are compatible with
all supported I/O standards. There is a P/N pin pair for
support of differential I/O standards. Single-ended clock
I/Os can only be assigned to the P side of a paired I/O.
The clock input is buffered prior to clocking the R-cells.
When the CLK pins are unused, Actel recommends that
they are tied to ground.
1.5V Supply
REF
CCPLX
Supply Voltage
Dedicated (Hardwired) Clocks A, B, C
and D
Routed Clocks E, F, G, and H
250 Ω
and V
10µf
COMPLX
2-89.
0.1µf
Power Supply Connect
Axcelerator Family FPGAs
REF
pins are configured
REF
Axcelerator Chip
pins are not in
REF
V
V
CCPLX
pins in an
COMPLX
2-9