AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 103

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Building RAM and FIFO Modules
RAM and FIFO modules can be generated and included
in a design in two different ways:
Other Architectural Features
Low Power Mode
Although designed for high performance, the AX
architecture also allows the user to place the device into
a low power mode. Each I/O bank in an Axcelerator
device can be configured individually, when in low
power mode, to tristate all outputs, disable inputs, or
both. The low power mode is activated by asserting the
LP pin, which is grounded in normal operation.
While in the low power mode, the device is still fully
functional and all internal logic states are preserved. This
allows a user to disable all but a few signals and operate
the part in a low-frequency, watchdog mode if desired.
Please note, if the I/O bank is not disabled, differential I/Os
belonging to the I/O bank will still consume normal
power, even when operating in the low power mode.
The Axcelerator device will resume normal operation
10μs after the LP pin is pulled Low.
To further reduce power consumption, the internal
charge pump can be bypassed and an external power
supply voltage can be used instead. This saves the
internal charge-pump operating current, resulting in no
DC current draw. The Axcelerator family devices have a
dedicated "V
external charge pump device. In normal chip operation,
when using the internal charge pump, V
tied to GND. When the voltage level on V
3.3V, the internal charge pump is turned off, and the
V
Adequate voltage regulation (i.e. high drive, low output
impedance, and good decoupling) should be used at
V
In addition, any PLL in use can be powered down to
further reduce power consumption. This can be done
with the PowerDown pin driven Low. Driving this pin
High restarts the PLL with the output clock(s) being
stable once lock is restored.
PUMP
PUMP
• Using the SmartGen Core Generator where the
• The alternative is to instantiate the RAM/FIFO
.
user defines the depth and width of the FIFO/
RAM, and then instantiates this block into the
design
FlashROM, Analog System Builder, and Flash
Memory System Builder
information).
blocks manually, using inverters for polarity
control and tying all unused data bits to ground.
voltage will be used as the charge pump voltage.
PUMP
(please
" pin that can be used to access an
refer
to
User’s Guide for more
Actel’s
PUMP
PUMP
SmartGen,
should be
is set to
v2.7
JTAG
Axcelerator offers a JTAG interface that is compliant with
the IEEE 1149.1 standard. The user can employ the JTAG
interface for probing a design and performing any JTAG
Public Instructions as defined in the
Interface
The interface consists of four inputs: Test Mode Select
(TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller
Reset (TRST), and an output, Test Data Out (TDO). TMS,
TDI, and TRST have on-chip pull-up resistors.
Table 2-102 • JTAG Instruction Code
TRST
TRST (Test-Logic Reset) is an active-low, asynchronous
reset signal to the TAP controller. The TRST input can be
used to reset the Test Access Port (TAP) Controller to the
TRST state. The TAP Controller can be held at this state
permanently by grounding the TRST pin. To hold the
JTAG TAP controller in the TRST state, it is recommended
to connect TRST to ground via a 1 kΩ resistor.
There is an optional internal pull-up resistor available for
the TRST input that can be set by the user at
programming. Care should be exercised when using this
option in combination with an external tie-off to
ground.
An on-chip power-on-reset (POWRST) circuit is included.
POWRST has the same function as "TRST," but it only
occurs at power-up or during recovery from a V
or V
TDO
TDO is normally tristated, and it is active only when the
TAP controller is in the "Shift_DR" state or "Shift_IR"
state. The least significant bit of the selected register (i.e.
IR or DR) is clocked out to TDO first by the falling edge of
TCK.
TAP Controller
The TAP Controller is compliant with the IEEE Standard
1149.1. It is a state machine of 16 states that controls the
Instruction (IR4:IR0)
Extest
Preload / Sample
Intest
USERCODE
IDCODE
HIGHZ
CLAMP
Diagnostic
Reserved
Bypass
CCDA
voltage drop.
Axcelerator Family FPGAs
Table
Binary Code
2-102.
All others
00000
00001
00010
00011
00100
01110
01111
10000
11111
CCA
and/
2-89