AX500-1BG896 ACTEL [Actel Corporation], AX500-1BG896 Datasheet - Page 94

• Manufacturer Part Number: AX500-1BG896
• Description: Axcelerator Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

FIFO
Every memory block has its own embedded FIFO
controller. Each FIFO block has one read port and one
write port. This embedded FIFO controller uses no
internal FPGA logic and features:
Both ports are configurable in various sizes from 4k x 1
to 128 x 36, similar to the RAM block size. Each port is
fully synchronous.
Read
independent. Data on the appropriate WD pins are
written to the FIFO on every active WCLK edge as long as
WEN is high. Data is read from the FIFO and output on
the appropriate RD pins on every active RCLK edge as
long as REN is asserted.
Figure 2-61 • Axcelerator RAM with Embedded FIFO Controller
2 -8 0
Axcelerator Family FPGAs
• Glitch-free FIFO Flags
• Gray-code address counters/pointers to prevent
• Overflow and underflow control
DEPTH[3:0]
metastability problems
and
FWEN
FREN
CLR
write
operations
WCLK
RCLK
WD
can
be
CNT 16
E
CNT 16
E
completely
v2.7
The FIFO block offers programmable almost-empty
(AEMPTY) and almost-full (AFULL) flags as well as EMPTY
and FULL flags
Gray code counters are used to prevent metastability
problems associated with flag logic. The depth of the
FIFO is dependent on the data width and the number of
memory blocks used to create the FIFO. The write
operations to the FIFO are synchronous with respect to
the WCLK, and the read operations are synchronous with
respect to the RCLK.
The FIFO block may be reset to the empty state.
AEVAL
AFVAL
• The FULL flag is synchronous to WCLK. It allows
• The EMPTY flag is synchronous to RCLK. It allows
=
=
the FIFO to inhibit writing when full.
the FIFO to inhibit reading at the empty condition.
> =
>
(Figure
WD [n-1:0]
RCLK
WCLK
RA [J:0]
WA [J:0]
REN
WEN
FULL
AFULL
AEMPTY
EMPTY
2-61):
RAM
RD [n-1:0]
RD