LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet - Page 18

• Manufacturer Part Number: LC89057W-VF4A-E
• Description: Digital Audio Interface Transceiver
• Manufacturer: SANYO [Sanyo Semicon Device]

10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
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The relationships between the output clock and switch function are shown below.
PLL in the figure indicates the PLL source (or TMCK source), and XIN the XIN source.
The contents in the square brackets [∗∗∗] by the switch function blocks correspond to the write command names.
The broken lines connecting the switches indicate coordinated switching.
Lock/Unlock is switched automatically by PLL locking/unlocking.
Master/Slave is switched by master/slave function switching of demodulation function.
XTAL Source
PLL Source
TMCK Source
12.288MHz or 24.576MHz
Master Clock
256fs or 512fs
256fs or 512fs
Generator
512fs / 256fs
256fs / 128fs
128fs / 64fs
MUTE
MUTE
128fs
64fs
32fs
12.288MHz / 24.576MHz
12.288MHz / 24.576MHz
fs/2
6.144MHz / 12.288MHz
Figure 10.3 Clock Output Block Diagram
6.144MHz / 12.288MHz
2fs
3.072MHz / 6.144MHz
fs
MUTE
12.288MHz
6.144MHz
3.072MHz
12.288MHz
6.144MHz
3.072MHz
192kHz
LC89057W-VF4A-E
192kHz
96kHz
48kHz
[PSBCK]
96kHz
48kHz
MUTE
MUTE
MUTE
MUTE
[PSLRCK]
[PRSEL]
MUTE
MUTE
to internal circuits
[XRBCK]
[XSBCK]
[XRLRCK]
[XSLRCK]
PLL 64fs
PLL fs
[XRSEL]
[XMSEL]
Lock / Unlock
PLL
XIN
PLL
XIN
PLL
XIN
PLL
XIN
PLL
XIN
XIN
[OCKSEL] ([SELMTD]=0)
[RCKSEL] ([SELMTD]=1)
Master / Slave
[SELMTD]
RLRCK (I/O)
RBCK (I/O)
XMCK (O)
SLRCK (O)
SBCK (O)
RMCK (O)
No.7202-18/59