LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet - Page 26

• Manufacturer Part Number: LC89057W-VF4A-E
• Description: Digital Audio Interface Transceiver
• Manufacturer: SANYO [Sanyo Semicon Device]

10.4 Error Output Processing
10.4.1 Lock error and data error output (RERR)
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10.4.2 PLL lock error
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10.4.3 Input data parity error
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10.4.4 Other errors
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the previous block is compared with the current data. Moreover, the input data sampling frequency is calculated from
the fs clock extracted from the input data, and the fs calculated value is compared in a same way as described above. If
any difference is detected in these data, RERR is instantly made "H" and the same processing as for PLL lock errors is
carried out.
variable fs (for example a CD player with a variable pitch function), it is possible to set with FSERR not to output an
error flag unless fs changes exceeding the PLL capture range.
Moreover, in the FSERR setting, when the PLL is locked, RERR is turned to “L” without reflecting the fs calculation
data input is detected. At this time, the PLL locked status and various output clocks are subject to the input data, but
the output data is muted.
RERR outputs an error flag when a PLL lock error or a data error occurs.
It is possible to treat non-PCM data reception as an error by the RESEL setting.
The RERR output conditions are set with RESTA. Since the PLL status can be output at all times, the PLL status can
The PLL gets unlocked for input data that lost bi-phase modulation regularity, or input data for which preambles B, M,
and W cannot be detected.
RERR turns to "H" upon occurrence of a PLL lock error, and returns to "L" when data demodulation returns to normal
and "H" is maintained for somewhere between 45ms and 300ms.
The rising and falling edges of RERR are synchronized with RLRCK.
Odd number of errors among parity bits in input data and input parity errors are detected.
If an input parity error occurs 9 or more times in succession, RERR turns to "H" indicating that the PLL is locked, and
after holding "H" for somewhere between 45ms and 300ms, it returns to "L".
The error flag output format can be selected with REDER, when an input parity error is output less than 9 times in
succession.
Even if RERR turns to "L", the channel status bits of 24 to 27 (sampling frequency) are always fetched and the data of
The PLL causes a lock error when the fs changes as described above. However, in order to support sources with a
result to the error flag concerning input data within reception range by FSLIM[1:0].
If a setting which regard non-PCM data input as an error is made with RESEL, RERR turns to “H” when non-PCM
be always monitored, even when the clock source is XIN.
LC89057W-VF4A-E
No.7202-26/59