LC89057W-VF4A-E SANYO [Sanyo Semicon Device], LC89057W-VF4A-E Datasheet - Page 28

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LC89057W-VF4A-E

Manufacturer Part Number
LC89057W-VF4A-E
Description
Digital Audio Interface Transceiver
Manufacturer
SANYO [Sanyo Semicon Device]
Datasheet

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10.4.6 Processing during error recovery
10.5 Channel Status Data Output
10.5.1 Data delimiter bit 1 output (
10.5.2 Emphasis information output (EMPHA)
EMPHA is immediately output upon detection of RERR even during "H" output.
When preambles B, M, and W are detected, PLL becomes locked and data demodulation begins.
RDATA output data is output from the RLRCK edge after RERR turns to "L".
AUDIO outputs bit 1 of the channel status that indicates whether the input bi-phase data is PCM audio data.
OR-output with IEC61937 or with the DTS-CD/LD detection flag is also possible with AOSEL.
EMPHA outputs shows whether there are 50/15μs emphasis parameters for consumer and broadcast studio.
immediately output upon detection of RERR even during "H" output period.
____________
Internal lock signal
RLRCK
RDATA
RERR
Figure 10.12 Data processing when data demodulation starts
______
EMPHA
AUDIO
H
L
H
L
________
AUDIO )
LC89057W-VF4A-E
Table 10.7 EMPHA Output
Table 10.6
OK
Output start from RLRCK edge
immediately after RERR flag is lowered
AUDIO Output
____________
45ms to 300ms
PCM audio data (CS bit 1 = "L")
Non-audio data (CS bit 1 = "H")
50/15μs pre-emphasis
Output Conditions
Output Conditions
No pre-emphasis
Data
No.7202-28/59
AUDIO is
____________

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