LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 17

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

9. Description of Analog to Digital Converter (ADC)
9.1 Operation Settings
• ADC operation can be selected from the automatic stop mode that follows DIR operation, continuous operation mode,
9.1.1 Automatic Stop Mode
• The automatic stop mode function sets ADC operation with priority on the DIR status, and controls ADC operation
• The ADC is automatically set to the reset status in the PLL locked status. When the PLL changes to the unlocked
• When setting the ADC to automatic stop mode, it is recommended to simultaneously make the oscillation amplifier
9.1.2 Continuous Operation Mode
• The ADC can be set to the continuous operation mode that constantly continues analog to digital conversion operation
• Continuous operation mode can be set in the following states. This setting has priority over automatic stop mode.
9.1.3 Low Sampling Rate Operation Mode
• The low sampling rate operation mode performs analog audio data detection with low power consumption.
• To set this mode, both “ADCOPR[1:0]=10” and “SDMODE=1” must be set. These registers need to detect the
• Low sampling rate operation mode operates only when set to master mode. When the ADC is operated in slave mode,
• After this mode is set, the ADC performs analog to digital conversion at a sampling rate of 6kHz.
• Current consumption can be further reduced by simultaneously setting to stop the DIR function and fix the output
Automatic stop mode (initial value)
Continuous operation mode
Low sampling rate operation mode
Power-down mode
status, the reset is canceled and the ADC restarts analog to digital conversion. However, ADC is set to the reset status
when ERRF is “H” and PLL is locked. (when “RXRESEL=1” or “RXRESTA=1”)
stop setting. The oscillation amplifier can be automatically stopped while the PLL is locked, by “AMPOPR[1:0]=01”.
This eliminates the possibility of coexistence of the XIN clock and PLL clock, enabling reduction of interference
between the clocks. However, this excludes cases when the XIN clock cannot be stopped, such as when the oscillation
amplifier clock output XMCK is constantly supplied to the DSP, etc.
regardless of the DIR status.
existence of analog audio data in power save operation. When only the ADCOPR[1:0] register or the SDMODE
register is set, this function does not operate.
low sampling rate operation cannot be set.
clock pin outputs to suppress current consumption other than the ADC. See below for further details, “9.6 Analog
Audio Data Detection”.
according to the PLL locked status and ERRF output status. (“ADCOPR[1:0]=00”)
low sampling rate operation mode, and power-down mode. The initial value is set to the automatic stop mode that
follows DIR operation.
- When the ADC clock and data are set to constant output: “SW1SEL[2:0]=001” or “SW2SEL[2:0]=001”
- When ADC slave operation is set: “MPSEL[1:0]=10 or 11”
(Analog Audio Data Detection in Power Save Operation Mode)
Mode Setting
Table 9.1 ADC Operation Mode Comparison
LC89075W-H
When PLL is unlocked: Operating
When PLL is locked: Reset (ADC also resets when ERRF is “H” and PLL is locked)
Always operating
Operating (ADC’s rate fixed at 6kHz)
Complete stop
ADC State
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