LC89075W-H SANYO [Sanyo Semicon Device], LC89075W-H Datasheet - Page 28

• Manufacturer Part Number: LC89075W-H
• Description: Digital Audio Interface Receiver with Stereo ADC and Audio Selector
• Manufacturer: SANYO [Sanyo Semicon Device]

10.1.5 Output Clocks Generated When Input S/PDIF Reception is Limited
• The input S/PDIF reception range can be set with the RXLIM[1:0] register.
• If an S/PDIF input that exceeds the reception range limit is supplied, the same processing is performed as when the
PLL is unlocked. The clock source is then switched to the XIN clock, and clocks are output from respective clock pins.
PLL status
PLL status
PLL status
LRCKOUT
LRCKOUT
LRCKOUT
MCKOUT
MCKOUT
MCKOUT
BCKOUT
BCKOUT
BCKOUT
RXIN**
RXIN**
RXIN**
ERRF
ERRF
ERRF
Figure 10.4 Output Clocks Generated When Input Data Reception Is Limited
Fs=44.1kHz
Fs=44.1kHz
Fs=44.1kHz
(b) When set to “RXLIM[1:0]=01” (Receive frequency is limited to 96kHz or lower)
(c) When set to “RXLIM[1:0]=10” (Receive frequency is limited to 48kHz or lower)
PLL clock
PLL clock
PLL clock
LOCK
LOCK
LOCK
(a) When set to “RXLIM[1:0]=00” (No limit on inputs)
LC89075W-H
Fs=192kHz
Fs=192kHz
Fs=192kHz
XIN clock
PLL clock
LOCK
LOCK
LOCK
XIN clock
XIN clock
UNLOCK
Fs=96kHz
Fs=96kHz
Fs=96kHz
PLL clock
PLL clock
LOCK
LOCK
LOCK
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