HY5DU561622CT-D HYNIX [Hynix Semiconductor], HY5DU561622CT-D Datasheet - Page 29

• Manufacturer Part Number: HY5DU561622CT-D
• Description: 256M-P DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

AC CHARACTERISTICS I
Rev. 0.3 / Oct. 2003
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Active to Read with Auto Precharge Delay
Row Address to Column Address Delay
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Write to Read Command Delay
Auto Precharge Write Recovery + Precharge Time
System Clock Cycle Time
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Data-out high-impedance window from CK,/CK
Data-out low-impedance window from CK, /CK
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Parameter
(AC operating conditions unless otherwise noted)
CL = 3
Symbol
tDQSCK
tDQSQ
tWTR
tRCD
tRRD
tCCD
tQHS
tRFC
tRAS
tRAP
tDAL
tWR
tQH
tRC
tCH
tAC
tHP
tHZ
tRP
tCK
tCL
tLZ
tIS
tIH
t
t
IH
IS
(tCL,tCH)
(tWR/tCK)
tRAS(min)
tAC(min) tAC(Max) tAC(min)
(tRP/tCK)
tRCD or
-t
-0.65
-0.55
0.45
0.45
Min
DDR400 (D4)
min
t
0.6
0.6
0.7
0.7
58
70
40
18
18
15
10
QHS
HP
1
2
+
5
-
-
tAC(Max)
Max
0.55
0.55
0.65
0.55
70K
0.4
0.5
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(tCL,tCH)
tRAS(min)
(tWR/tCK)
(tRP/tCK)
tRCD or
HY5DU561622CT-D4/D43
-t
DDR400 (D43)
-0.65
-0.55
Min
0.45
0.45
min
t
0.6
0.6
0.7
0.7
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
55
70
40
15
10
15
15
QHS
+
HP
1
2
5
-
-
tAC(Max)
tAC(Max)
Max
0.55
0.55
0.65
0.55
70K
0.4
0.5
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
CK
CK
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2,3,5,6
2,4,5,6
Note
1,10
1,9
16
15
10
17
29