HY5DU561622CT-D HYNIX [Hynix Semiconductor], HY5DU561622CT-D Datasheet - Page 32

• Manufacturer Part Number: HY5DU561622CT-D
• Description: 256M-P DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
Rev. 0.3 / Oct. 2003
transitions through the DC region must be monotonic.
tCK is equal to the actual system clock cycle time.
Example: For DDR400(D4) at CL=3 and tCK = 5.0 ns,
tDAL = (15 ns / 5.0 ns) + (18 ns / 5.0 ns) = (3.00) + (3.6)
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7 clocks
tRAS - (BL/2) x tCK.
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
HY5DU561622CT-D4/D43
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
32