CH7007A-V ETC, CH7007A-V Datasheet - Page 43

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CH7007A-V

Manufacturer Part Number
CH7007A-V
Description
DIGITAL PC TO TV ENCODER WITH MACROVISION
Manufacturer
ETC
Datasheet
CHRONTEL
Register Descriptions (continued)
PLL Control Register
The following PLL and memory controls are available through the PLL control register:
MEM5V
PLL5VA
PLL5VD
PLLS
PLLCAP
PLLCPI
201-0000-002 Rev. 2.7, 08/23/2000
Bit:
Symbol:
Type:
Default:
7
MEM5V should be set to 0 when DVDD is 3.3 volts, and 1 when DVDD is 5 volts.
PLL5VA is set to 1 when AVDD is 5 volts.
PLL5VD is set to 1 when DVDD is 5 volts. A value of 0 is used when DVDD is 3.3 volts (default).
When the PLL5VA is 1 PLLS should be 1. When PLL5VA is 0 PLLS should be 0.
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs
Mode is shown below.
The default value should be used.
6
5
PLLCPI
R/W
0
4
PLLCAP
R/W
0
3
PLLS
R/W
1
2
PLL5VD
0
R/W
Symbol: PLLC
Address: 20H
Bits: 6
1
PLL5VA
R/W
1
CH7007A
0
MEM5V
R/W
0
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