AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 19

• Manufacturer Part Number: AM186CC-50KC\W C
• Manufacturer: AMD

Signal Name
POWER AND GROUND
V
V
V
V
V
V
DEBUG SUPPORT
QS1–QS0
The following signals are also used by emulators: A19–A0, AD15–AD0, {ADEN}, ALE, ARDY, BHE, BSIZE8, CAS1–CAS0,
CLKOUT, {CLKSEL2–CLKSEL1}, HLDA, HOLD, LCS, MCS3–MCS0, NMI, {ONCE}, QS1–QS0, RAS1–RAS0, RD, RES,
RESOUT, S2–S0, S6, SRDY, UCS, {UCSX8}, V
Manual , order #21914, for more information.
CHIP SELECTS
LCS
[MCS3]
MCS2
MCS1
[MCS0]
CC
SS
CC
CC
SS
SS
_USB (1)
_USB (1)
(15)
_A (1)
(15)
_A (1)
Multiplexed
Signal(s)
—
—
—
—
—
—
—
[RAS0]
[RAS1]
PIO5
[CAS0]
[CAS1]
{UCSX8}
PIO4
Am186™CC Communications Controller Data Sheet
Table 4. Signal Descriptions (Continued)
Type Description
STI
STI
STI
STI
STI
STI
O
O
O
Digital Power Supply pins supply power (+3.3 ± 0.3 V) to the Am186CC
controller logic.
Analog Power Supply pin supplies power (+3.3 ± 0.3 V) to the oscillators and
PLLs.
USB Power Supply pin supplies power (+3.3 ± 0.3 V) to the USB block.
Digital Ground pins connect the Am186CC controller logic to the system
ground.
Analog Ground pin connects the oscillators and PLLs to the system ground.
USB Ground pin connects the USB block to the system ground.
Queue Status 1–0 values provide information to the system concerning the
interaction of the CPU and the instruction queue. The pins have the following
meanings:
Lower Memory Chip Select indicates to the system that a memory access is in
progress to the lower memory block. The base address and size of the lower
memory block are programmable up to 512 Kbyte. LCS can be configured for 8-
bit or 16-bit bus size. LCS is three-stated with a pullup resistor during bus-hold
or reset conditions.
Midrange Memory Chip Selects 3–0 indicate to the system that a memory
access is in progress to the corresponding region of the midrange memory block.
The base address and size of the midrange memory block are programmable.
The midrange chip selects can be configured for 8-bit or 16-bit bus size. The
midrange chip selects are three-stated with pullup resistors during bus-hold or
reset conditions.
[MCS0] can be programmed as the chip select for the entire middle chip select
address range.
Unlike the UCS and LCS chip selects that operate relative to the earlier timing of
the nonmultiplexed A address bus, the MCS outputs assert with the multiplexed
AD address and data bus timing.
CC
, WHB, WLB, WR. See the Am186™CC/CH/CU Microcontrollers User’s
QS1 QS0 Queue Operation
0
0
1
1
0
1
0
1
None
First opcode byte fetched from queue
Queue was initialized
Subsequent byte fetched from queue
Queue Status Pins
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