AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 65

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AM186CC-50KC\W C

Manufacturer Part Number
AM186CC-50KC\W C
Description
Manufacturer
AMD
Datasheet
Notes:
1. All timing parameters are measured at V
2. PIO outputs change anywhere from the beginning of T3 to the first half of T4 of the bus cycle in which the PIO data register is
No.
53
54
55
56
are with the load values shown in Table 35, “Pin List Summary,” on page A-12.
written.
INT8–INT0, NMI, TMRINx
Symbol
t
t
t
CHQ0SV
CHQ1SV
t
CLTMV
INVCH
DRQ0, DRQ1
TMROUT
CLKOUT
Description
Peripheral setup time
Timer output delay
Queue status 0 output delay
Queue status 1 output delay
QS0
QS1
Parameter
Am186™CC Communications Controller Data Sheet
Figure 20. Peripheral Timing Waveforms
CC
Table 14. Peripheral Timing
/2 with 50-pF loading on CLKOUT unless otherwise noted. All output test conditions
Min
10
25 MHz
53
Max
25
25
25
54
1, 2
Min
5
40 MHz
Preliminary
56
Max
15
15
15
55
(Commercial Only)
Min
5
50 MHz
Max
12
12
12
Unit
ns
ns
ns
ns
65

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