AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 61

• Manufacturer Part Number: AM186CC-50KC\W C
• Manufacturer: AMD

General Timing Responses
No.
10
11
12
13
14
16
17
18
19
20
21
23
3
4
5
6
7
8
9
Symbol Description
t
t
t
t
t
t
t
CHCSX
t
t
t
t
t
CLCSV
CXCSX
t
CVCTV
CVDEX
t
t
t
t
t
t
CHSV
CHDX
CLSH
CLAX
CLDV
CHLH
AVCH
DXDL
CLAV
CHLL
LLAX
LHAV
LHLL
AVLL
Parameter
Status active delay
Status and BHE
inactive delay
AD address and
BHE valid delay
Address hold
Data valid delay
Status hold time
ALE active delay
ALE width
ALE inactive delay
AD address valid
to ALE Low
AD address hold
from ALE inactive
AD address valid
to clock High
MCS/PCS active
delay
MCS/PCS hold
from command
inactive
MCS/PCS inactive
delay
DEN inactive to
DT/R
Control active
delay 1
DS inactive
delay
ALE High to
address valid
2, 3
3,4
3,4
2
Am186™CC Communications Controller Data Sheet
t
CLCL
0.5 • t
Table 12. Write Cycle Timing
t
t
CHCL
CLCH
Min
– 10 = 30
–1
15
—
—
0
0
0
0
0
0
0
0
0
0
0
25 MHz
CLCH
Max
20
20
20
20
20
20
20
20
20
20
—
—
—
—
—
—
—
—
—
t
CLCL
0.5 • t
t
t
CHCL
CLCH
Preliminary
Min
7.5
– 5 = 20
–1
—
—
0
0
0
0
0
0
0
0
0
0
0
40 MHz
CLCH
1
Max
12
12
12
12
12
12
12
12
12
12
—
—
—
—
—
—
—
—
—
t
CLCL
(Commercial Only)
0.5 • t
t
t
Min
CHCL
CLCH
–1
—
– 5 = 15
—
0
0
0
0
0
0
0
0
0
0
0
5
50 MHz
CLCH
Max
10
10
10
—
10
10
—
10
—
—
—
10
—
10
—
10
10
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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